xref: /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala (revision b52d475534795fe5ff9bc9107eb7a4d1b6966d85) 
1package xiangshan.backend.fu.vector
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util.{BitPat, log2Up}
6import xiangshan.XSCoreParamsKey
7import xiangshan.backend.decode.isa.bitfield.InstVType
8
9object Bundles {
10
11  /**
12    * vtype bundle, should not used as csr reg
13    */
14  class VType extends Bundle {
15    val illegal = Bool()
16    val vma     = Bool()
17    val vta     = Bool()
18    val vsew    = VSew()
19    val vlmul   = VLmul()
20  }
21
22  object VType {
23    def apply() : VType = {
24      new VType
25    }
26
27    def fromInstVType(instVType: InstVType) : VType = {
28      val res = Wire(VType())
29      res.vma   := instVType.vma
30      res.vta   := instVType.vta
31      res.vsew  := instVType.vsew(VSew.width - 1, 0)
32      res.vlmul := instVType.vlmul
33      res.illegal := false.B // Todo: add illegal check function
34      res
35    }
36  }
37
38  class VConfig(implicit p: Parameters) extends Bundle {
39    val vl    = Vl()
40    val vtype = new VType
41  }
42
43  object VConfig {
44    def apply()(implicit p: Parameters) : VConfig = {
45      new VConfig()
46    }
47  }
48
49  def mu: UInt = 0.U(1.W)
50  def ma: UInt = 1.U(1.W)
51  def tu: UInt = 0.U(1.W)
52  def ta: UInt = 1.U(1.W)
53
54  object VSew {
55    def apply(): UInt = UInt(width.W)
56
57    def width = 2 // modify it when support more vector data width
58
59    def e8  : UInt = "b000".U(width.W)
60    def e16 : UInt = "b001".U(width.W)
61    def e32 : UInt = "b010".U(width.W)
62    def e64 : UInt = "b011".U(width.W)
63
64    def reserved: BitPat = BitPat("b1??")
65
66    def isReserved(sew: UInt) : Bool = {
67      require(sew.getWidth >= 2 && sew.getWidth <= 3)
68      if (sew.getWidth == 3) {
69        sew === reserved
70      } else {
71        false.B
72      }
73    }
74  }
75
76  object VLmul {
77    def apply(): UInt = UInt(width.W)
78
79    def width = 3
80
81    def m1  : UInt = "b000".U(width.W)
82    def m2  : UInt = "b001".U(width.W)
83    def m4  : UInt = "b010".U(width.W)
84    def m8  : UInt = "b011".U(width.W)
85    def mf2 : UInt = "b111".U(width.W)
86    def mf4 : UInt = "b110".U(width.W)
87    def mf8 : UInt = "b101".U(width.W)
88
89    def reserved: BitPat = BitPat("b100")
90
91    def isReserved(vlmul: UInt) : Bool = {
92      require(vlmul.getWidth == 3)
93      vlmul === reserved
94    }
95  }
96
97  object Vl {
98    def apply()(implicit p: Parameters): UInt = UInt(width.W)
99
100    def width(implicit p: Parameters) = p(XSCoreParamsKey).vlWidth
101  }
102}
103