fix(fof): always use tail undisturbed when vl updated by un-raised exception.

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merg

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merge will be handled first, and then the registers needed to move will be handled later.
* The need merge vdIdx can be until 8, so 4 bits reg is needed.
* If the instruction is indexed, the eew of vd is sew from vtype. Otherwise, the eew of vd is encoded in instruction.
* Use ivemulNoLessThanM1 and dvemulNoLessThanM1 to produce vemul_i_d to avoid either demul or iemul is less than M1.
* For whole register load, need handle NF(nf + 1) dest regs.
* Use data EMUL to calculate number of dest reg.
* GetE8OffsetInVreg will return the n-th 8bit which idx mapped to.
* Since xs will flush pipe, when vstart is not 0 and execute vector mem inst, the value of vstart in CSR is the
first element of this vector instruction. When exception occurs, the vstart in writeback bundle is the new one,
So writebacked vstart should never be used as the beginning of vector mem operation.
* Non-seg indexed load use non-sequential vd.
* When "index emul" / "data emul" equals 2,
the old vd is located in vuopidx 0, 2, 4, 6,
the new vd is located in vuopidx 1, 3, 5, 7.
* Make rename's input not ready until VecExcpMod not busy.
* Delay trap passed to difftest until VecExcpMod not busy.
* Rab commit to VecExcpMod as it commit to Rat, and select real load reg maps in VecExcpMod.
* Use isDstMask to distinguish vlm and other vle.
* When isWhole, vd regs are sequential.

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vtype: init vtype's vill to 1 and other fields to 0

NewCSR: fix unprivileged CSRs and permission check

* Add commit vstart
* Fix commit connection
* Fix permission check
* Fix mstatus.VS/FS initial with off
* Add fp/vec.off bundle to decode
* Flush w

NewCSR: fix unprivileged CSRs and permission check

* Add commit vstart
* Fix commit connection
* Fix permission check
* Fix mstatus.VS/FS initial with off
* Add fp/vec.off bundle to decode
* Flush when change vxrm
* Add more skip condition for mip and hip

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rv64v: Modify the width of Veew when decode (#3213)

vtype: add illegal check when modified reserved bits of vtype (#3170)

rv64v: fix vwsll's imm read and illegal vsew check (#3131)

VLSU: fix numLsElem width and also make code more formal

Backend: support vector load&store better

* Todo: add more IQs for vector load&store
* Todo: make vector memory inst issue out of order
* Todo: fix bugs

rv64v: add f2v to remove all fs1 duplicate logic (#2613)

* rv64v: add f2v to remove all fs1 duplicate logic

* rv64v: use IntFPToVec module for i2v and f2v

backend,vset: fix VConfig bundle

* vl should be located at low bits

rv64v: add veew in VPUCtrlSignals (#2434)

rv64v: support all opivi instructions use i2v

rv64v: replace i2f by i2v for vector instructions

fix merge error

backend: support unordered vfreduction

exu: vector float units(vfalu,vfma,vfdivsqrt) execute scalar float instructions

vector: add the connection for permutation

vector: add scala data duplicated to vector data path

fu,vector: add bundles used by vector units

backend: refactor vset and add rab support

isa-riscv,vector: add bundles and convert function

* Add class VType, VConfig
* Add object VSew, VLmul