1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import chisel3.experimental.chiselName 25 26trait BimParams extends HasXSParameter { 27 val BimBanks = PredictWidth 28 val BimSize = 4096 29 val nRows = BimSize / BimBanks 30 val bypassEntries = 4 31} 32 33@chiselName 34class BIM(implicit p: Parameters) extends BasePredictor with BimParams { 35 class BIMResp extends Resp { 36 val ctrs = Vec(PredictWidth, UInt(2.W)) 37 } 38 class BIMMeta extends Meta { 39 val ctrs = Vec(PredictWidth, UInt(2.W)) 40 } 41 class BIMFromOthers extends FromOthers {} 42 43 class BIMIO(implicit p: Parameters) extends DefaultBasePredictorIO { 44 val resp = Output(new BIMResp) 45 val meta = Output(new BIMMeta) 46 } 47 48 override val io = IO(new BIMIO) 49 override val debug = true 50 51 val bimAddr = new TableAddr(log2Up(BimSize), BimBanks) 52 53 val bim = Module(new SRAMTemplate(UInt(2.W), set = nRows, way=BimBanks, shouldReset = false, holdRead = true)) 54 55 val doing_reset = RegInit(true.B) 56 val resetRow = RegInit(0.U(log2Ceil(nRows).W)) 57 resetRow := resetRow + doing_reset 58 when (resetRow === (nRows-1).U) { doing_reset := false.B } 59 60 val if1_packetAlignedPC = packetAligned(io.pc.bits) 61 val if2_pc = RegEnable(if1_packetAlignedPC, io.pc.valid) 62 63 val if1_mask = io.inMask 64 val if1_row = bimAddr.getBankIdx(if1_packetAlignedPC) 65 66 bim.io.r.req.valid := io.pc.valid 67 bim.io.r.req.bits.setIdx := if1_row 68 69 val if2_bimRead = bim.io.r.resp.data 70 val ctrlMask = Fill(if2_bimRead.getWidth, ctrl.bim_enable.asUInt).asTypeOf(if2_bimRead) 71 io.resp.ctrs := VecInit(if2_bimRead zip ctrlMask map {case (a, b) => a & b}) 72 io.meta.ctrs := if2_bimRead 73 74 val updateValid = RegNext(io.update.valid) 75 val u = RegNext(io.update.bits) 76 77 val updateRow = bimAddr.getBankIdx(u.ftqPC) 78 79 80 val wrbypass_ctrs = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(BimBanks, UInt(2.W))))) 81 val wrbypass_ctr_valids = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(BimBanks, Bool())))) 82 val wrbypass_rows = RegInit(0.U.asTypeOf(Vec(bypassEntries, UInt(log2Up(nRows).W)))) 83 val wrbypass_enq_idx = RegInit(0.U(log2Up(bypassEntries).W)) 84 85 val wrbypass_hits = VecInit((0 until bypassEntries).map( i => 86 !doing_reset && wrbypass_rows(i) === updateRow)) 87 val wrbypass_hit = wrbypass_hits.reduce(_||_) 88 val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) 89 90 val oldCtrs = VecInit((0 until BimBanks).map(b => 91 Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(b), 92 wrbypass_ctrs(wrbypass_hit_idx)(b), u.metas(b).bimCtr))) 93 94 val newTakens = VecInit((0 until BimBanks).map(b => u.cfiIndex.valid && u.cfiIndex.bits === b.U)) 95 val newCtrs = VecInit((0 until BimBanks).map(b => satUpdate(oldCtrs(b), 2, newTakens(b)))) 96 // val oldSaturated = newCtr === oldCtr 97 98 val needToUpdate = VecInit((0 until PredictWidth).map(i => updateValid && u.br_mask(i) && u.valids(i))) 99 100 when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))} 101 102 for (b <- 0 until BimBanks) { 103 when (needToUpdate.reduce(_||_)) { 104 when (wrbypass_hit) { 105 when (needToUpdate(b)) { 106 wrbypass_ctrs(wrbypass_hit_idx)(b) := newCtrs(b) 107 wrbypass_ctr_valids(wrbypass_hit_idx)(b) := true.B 108 } 109 }.otherwise { 110 wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B 111 when (needToUpdate(b)) { 112 wrbypass_ctr_valids(wrbypass_enq_idx)(b) := true.B 113 wrbypass_ctrs(wrbypass_enq_idx)(b) := newCtrs(b) 114 } 115 } 116 } 117 } 118 119 when (needToUpdate.reduce(_||_) && !wrbypass_hit) { 120 wrbypass_rows(wrbypass_enq_idx) := updateRow 121 wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0) 122 } 123 124 bim.io.w.apply( 125 valid = needToUpdate.asUInt.orR || doing_reset, 126 data = Mux(doing_reset, VecInit(Seq.fill(BimBanks)(2.U(2.W))), newCtrs), 127 setIdx = Mux(doing_reset, resetRow, updateRow), 128 waymask = Mux(doing_reset, Fill(BimBanks, "b1".U).asUInt, needToUpdate.asUInt) 129 ) 130 131 XSPerfAccumulate("bim_wrbypass_hit", needToUpdate.reduce(_||_) && wrbypass_hit) 132 XSPerfAccumulate("bim_wrbypass_enq", needToUpdate.reduce(_||_) && !wrbypass_hit) 133 134 if (BPUDebug && debug) { 135 val u = io.update.bits 136 XSDebug(doing_reset, "Reseting...\n") 137 XSDebug("[update] v=%d pc=%x valids=%b, tgt=%x\n", updateValid, u.ftqPC, u.valids.asUInt, u.target) 138 139 XSDebug("[update] brMask=%b, taken=%b isMisPred=%b\n", u.br_mask.asUInt, newTakens.asUInt, u.mispred.asUInt) 140 for (i <- 0 until BimBanks) { 141 XSDebug(RegNext(io.pc.valid && io.inMask(i)), p"BimResp[$i]: ctr = ${io.resp.ctrs(i)}\n") 142 XSDebug(needToUpdate(i), 143 p"update bim bank $i: pc:${Hexadecimal(u.ftqPC)}, taken:${u.takens(i)}, " + 144 p"oldCtr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n") 145 XSDebug(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(i) && needToUpdate(i), 146 p"bank $i wrbypass hit wridx $wrbypass_hit_idx: row:$updateRow, " + 147 p"ctr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n") 148 XSDebug(true.B, p"bimCtr(${i.U})=${Binary(u.metas(i).bimCtr)} oldCtr=${Binary(oldCtrs(i))} newCtr=${Binary(newCtrs(i))}\n") 149 } 150 } 151 152} 153