1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package system 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters} 23import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors} 24 25case object SoCParamsKey extends Field[SoCParameters] 26 27case class SoCParameters 28( 29 cores: List[XSCoreParameters], 30 EnableILA: Boolean = false, 31 extIntrs: Int = 150, 32 useFakeL3Cache: Boolean = false, 33 L3Size: Int = 4 * 1024 * 1024 // 4MB 34){ 35 val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y) 36 // L3 configurations 37 val L3InnerBusWidth = 256 38 val L3BlockSize = 64 39 val L3NBanks = 4 40 val L3NWays = 8 41 42 // on chip network configurations 43 val L3OuterBusWidth = 256 44 45} 46 47trait HasSoCParameter { 48 implicit val p: Parameters 49 50 val soc = p(SoCParamsKey) 51 val debugOpts = p(DebugOptionsKey) 52 val NumCores = soc.cores.size 53 val EnableILA = soc.EnableILA 54 55 // L3 configurations 56 val useFakeL3Cache = soc.useFakeL3Cache 57 val L3InnerBusWidth = soc.L3InnerBusWidth 58 val L3Size = soc.L3Size 59 val L3BlockSize = soc.L3BlockSize 60 val L3NBanks = soc.L3NBanks 61 val L3NWays = soc.L3NWays 62 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 63 64 // on chip network configurations 65 val L3OuterBusWidth = soc.L3OuterBusWidth 66 67 val NrExtIntr = soc.extIntrs 68} 69 70class ILABundle extends Bundle {} 71 72 73class L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 74 val paddr = Valid(UInt(soc.PAddrBits.W)) 75 // for now, we only detect ecc 76 val ecc_error = Valid(Bool()) 77} 78 79class XSL1BusErrors(val nCores: Int)(implicit val p: Parameters) extends BusErrors { 80 val icache = Vec(nCores, new L1CacheErrorInfo) 81 val l1plus = Vec(nCores, new L1CacheErrorInfo) 82 val dcache = Vec(nCores, new L1CacheErrorInfo) 83 84 override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] = 85 List.tabulate(nCores){i => 86 List( 87 Some(icache(i).paddr, s"IBUS_$i", s"Icache_$i bus error"), 88 Some(icache(i).ecc_error, s"I_ECC_$i", s"Icache_$i ecc error"), 89 Some(l1plus(i).paddr, s"L1PLUS_$i", s"L1PLUS_$i bus error"), 90 Some(l1plus(i).ecc_error, s"L1PLUS_ECC_$i", s"L1PLUS_$i ecc error"), 91 Some(dcache(i).paddr, s"DBUS_$i", s"Dcache_$i bus error"), 92 Some(dcache(i).ecc_error, s"D_ECC_$i", s"Dcache_$i ecc error") 93 ) 94 }.flatten 95} 96