xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala (revision c2650312b580f636dcbe07b8ba84fa3d8b9d3e3d) 
1package xiangshan.backend.fu.NewCSR.CSREvents
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{SignExt, ZeroExt}
7import xiangshan.{ExceptionNO, HasXSParameter}
8import xiangshan.ExceptionNO._
9import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState}
10import xiangshan.backend.fu.NewCSR.CSRConfig._
11import xiangshan.backend.fu.NewCSR.CSRDefines._
12import xiangshan.backend.fu.NewCSR._
13import xiangshan.backend.fu.util.CSRConst
14
15trait CSREvents { self: NewCSR =>
16  val trapEntryMEvent = Module(new TrapEntryMEventModule)
17
18  val trapEntryHSEvent = Module(new TrapEntryHSEventModule)
19
20  val trapEntryVSEvent = Module(new TrapEntryVSEventModule)
21
22  val mretEvent = Module(new MretEventModule)
23
24  val sretEvent = Module(new SretEventModule)
25
26  val events: Seq[Module with CSREventBase] = Seq(
27    trapEntryMEvent,
28    trapEntryHSEvent,
29    trapEntryVSEvent,
30    mretEvent,
31    sretEvent,
32  )
33
34  events.foreach(x => dontTouch(x.out))
35
36  val trapEntryEvents: Seq[Module with CSREventBase] = Seq(
37    trapEntryMEvent,
38    trapEntryHSEvent,
39    trapEntryVSEvent,
40  )
41}
42
43trait EventUpdatePrivStateOutput {
44  val privState = ValidIO(new PrivState)
45}
46
47trait EventOutputBase {
48  def getBundleByName(name: String): Valid[CSRBundle]
49}
50
51trait CSREventBase {
52  val valid = IO(Input(Bool()))
53  val in: Bundle
54  val out: Bundle
55}
56
57class TrapEntryEventInput(implicit val p: Parameters) extends Bundle with HasXSParameter {
58  val causeNO = Input(new CauseBundle)
59  val trapPc = Input(UInt(VaddrMaxWidth.W))
60  val isCrossPageIPF = Input(Bool())
61
62  // always current privilege
63  val iMode = Input(new PrivState())
64  // take MRPV into consideration
65  val dMode = Input(new PrivState())
66  // status
67  val privState = Input(new PrivState)
68  val mstatus = Input(new MstatusBundle)
69  val hstatus = Input(new HstatusBundle)
70  val sstatus = Input(new SstatusBundle)
71  val vsstatus = Input(new SstatusBundle)
72  val satp = Input(new SatpBundle)
73  val vsatp = Input(new SatpBundle)
74  // from mem
75  val memExceptionVAddr = Input(UInt(VAddrBits.W))
76  val memExceptionGPAddr = Input(UInt(GPAddrBits.W))
77}
78