1package xiangshan.backend.fu.wrapper 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.XSCoreParamsKey 8import xiangshan.backend.fu.vector.Bundles.{VConfig, VSew} 9import xiangshan.backend.fu.vector.{VecPipedFuncUnit} 10import xiangshan.backend.fu.vector.Utils.VecDataToMaskDataVec 11import xiangshan.backend.fu.{FuConfig, FuType} 12import yunsuan.{OpType, VialuFixType} 13import yunsuan.vector.alu.VIntFixpAlu 14import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType} 15import yunsuan.encoding.Opcode.VialuOpcode 16 17class VIAluSrcTypeIO extends Bundle { 18 val in = Input(new Bundle { 19 val fuOpType : UInt = OpType() 20 val vsew : UInt = VSew() 21 val isReverse : Bool = Bool() // vrsub, vrdiv 22 val isExt : Bool = Bool() 23 val isDstMask : Bool = Bool() // vvm, vvvm, mmm 24 val isMove : Bool = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 25 }) 26 val out = Output(new Bundle { 27 val vs1Type : UInt = Vs1IntType() 28 val vs2Type : UInt = Vs2IntType() 29 val vdType : UInt = VdType() 30 val illegal : Bool = Bool() 31 }) 32} 33 34class VIAluSrcTypeModule extends Module { 35 val io: VIAluSrcTypeIO = IO(new VIAluSrcTypeIO) 36 37 private val vsew = io.in.vsew 38 private val isExt = io.in.isExt 39 private val isDstMask = io.in.isDstMask 40 41 private val opcode = VialuFixType.getOpcode(io.in.fuOpType) 42 private val isSign = VialuFixType.isSigned(io.in.fuOpType) 43 private val format = VialuFixType.getFormat(io.in.fuOpType) 44 45 private val vsewX2 = vsew + 1.U 46 private val vsewF2 = vsew - 1.U 47 private val vsewF4 = vsew - 2.U 48 private val vsewF8 = vsew - 3.U 49 50 private val isAddSub = opcode === VialuOpcode.vadd || opcode === VialuOpcode.vsub 51 private val isShiftRight = Seq(VialuOpcode.vsrl, VialuOpcode.vsra, VialuOpcode.vssrl, VialuOpcode.vssra).map(fmt => fmt === format).reduce(_ || _) 52 private val isVext = opcode === VialuOpcode.vext 53 54 private val isWiden = isAddSub && Seq(VialuFixType.FMT.VVW, VialuFixType.FMT.WVW).map(fmt => fmt === format).reduce(_ || _) 55 private val isNarrow = isShiftRight && format === VialuFixType.FMT.WVV 56 private val isVextF2 = isVext && format === VialuFixType.FMT.VF2 57 private val isVextF4 = isVext && format === VialuFixType.FMT.VF4 58 private val isVextF8 = isVext && format === VialuFixType.FMT.VF8 59 60 // check illegal 61 private val widenIllegal = isWiden && vsewX2 === VSew.e8 62 private val narrowIllegal = isNarrow && vsewF2 === VSew.e64 63 private val vextIllegal = (isVextF2 && (vsewF2 === VSew.e64)) || 64 (isVextF4 && (vsewF4 === VSew.e64)) || 65 (isVextF8 && (vsewF8 === VSew.e64)) 66 // Todo: use it 67 private val illegal = widenIllegal || narrowIllegal || vextIllegal 68 69 private class Vs2Vs1VdSew extends Bundle { 70 val vs2 = VSew() 71 val vs1 = VSew() 72 val vd = VSew() 73 } 74 75 private val addSubSews = Mux1H(Seq( 76 (format === VialuFixType.FMT.VVV) -> Cat(vsew , vsew, vsew ), 77 (format === VialuFixType.FMT.VVW) -> Cat(vsew , vsew, vsewX2), 78 (format === VialuFixType.FMT.WVW) -> Cat(vsewX2, vsew, vsewX2), 79 (format === VialuFixType.FMT.WVV) -> Cat(vsewX2, vsew, vsew ), 80 )).asTypeOf(new Vs2Vs1VdSew) 81 82 private val vextSews = Mux1H(Seq( 83 (format === VialuFixType.FMT.VF2) -> Cat(vsewF2, vsewF2, vsew), 84 (format === VialuFixType.FMT.VF4) -> Cat(vsewF4, vsewF4, vsew), 85 (format === VialuFixType.FMT.VF8) -> Cat(vsewF8, vsewF8, vsew), 86 )).asTypeOf(new Vs2Vs1VdSew) 87 88 // Todo 89 private val maskSews = Mux1H(Seq( 90 (format === VialuFixType.FMT.VVMV) -> Cat(vsew, vsew, vsew), 91 (format === VialuFixType.FMT.VVM ) -> Cat(vsew, vsew, vsew), 92 (format === VialuFixType.FMT.MMM ) -> Cat(vsew, vsew, vsew), 93 )).asTypeOf(new Vs2Vs1VdSew) 94 95 private val vs2Type = Mux1H(Seq( 96 isExt -> Cat(0.U(1.W), isSign, vextSews.vs2), 97 (!isExt && !isDstMask) -> Cat(0.U(1.W), isSign, addSubSews.vs2), 98 )) 99 private val vs1Type = Mux1H(Seq( 100 isExt -> Cat(0.U(1.W), isSign, vextSews.vs1), 101 (!isExt && !isDstMask) -> Cat(0.U(1.W), isSign, addSubSews.vs1), 102 )) 103 private val vdType = Mux1H(Seq( 104 isExt -> Cat(0.U(1.W), isSign, vextSews.vd), 105 (!isExt && !isDstMask) -> Cat(0.U(1.W), isSign, addSubSews.vd), 106 )) 107 108 io.out.vs2Type := vs2Type 109 io.out.vs1Type := vs1Type 110 io.out.vdType := vdType 111 io.out.illegal := illegal 112} 113 114class VIAluFix(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 115 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VialuFixType.dummy, "VialuF OpType not supported") 116 117 // modules 118 119 private val typeModule = Module(new VIAluSrcTypeModule) 120 private val vIntFixpAlu = Module(new VIntFixpAlu) 121 122 val maskDataVec: Vec[UInt] = VecDataToMaskDataVec(srcMask) 123 val maskIdx = Mux(isNarrow, (vuopIdx >> 1.U).asUInt, vuopIdx) 124 val maskUsed = maskDataVec(maskIdx) 125 126 val vconfig = srcVConfig 127 val vl = vconfig.vl 128 129 130 /** 131 * [[typeModule]]'s io connection 132 */ 133 typeModule.io.in.fuOpType := fuOpType 134 typeModule.io.in.vsew := vsew 135 typeModule.io.in.isReverse := isReverse 136 typeModule.io.in.isExt := isExt 137 typeModule.io.in.isDstMask := vecCtrl.isDstMask 138 typeModule.io.in.isMove := isMove 139 140 /** 141 * [[vIntFixpAlu]]'s io connection 142 */ 143 vIntFixpAlu.io match { 144 case subIO => 145 subIO.in.opcode := VialuFixType.getOpcode(inCtrl.fuOpType).asTypeOf(subIO.in.opcode) 146 subIO.in.info.vm := vm 147 subIO.in.info.ma := vma 148 subIO.in.info.ta := vta 149 subIO.in.info.vlmul := vlmul 150 subIO.in.info.vl := srcVConfig.vl 151 subIO.in.info.vstart := vstart 152 subIO.in.info.uopIdx := vuopIdx 153 subIO.in.info.vxrm := vxrm 154 subIO.in.srcType(0) := typeModule.io.out.vs2Type 155 subIO.in.srcType(1) := typeModule.io.out.vs1Type 156 subIO.in.vdType := typeModule.io.out.vdType 157 subIO.in.vs2 := inData.src(0) 158 subIO.in.vs1 := inData.src(1) 159 subIO.in.old_vd := inData.src(2) 160 subIO.in.mask16b := maskUsed // Todo: make mask16b more flexiable 161 subIO.ctrl.narrow := isNarrow 162 subIO.ctrl.vstart_gte_vl := vstart >= vl 163 } 164 165 io.out.bits.res.data := vIntFixpAlu.io.out.vd 166 io.out.bits.res.vxsat.foreach(_ := vIntFixpAlu.io.out.vxsat) 167} 168