1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, MemExuOutput} 26import xiangshan.cache._ 27import xiangshan.cache.{DCacheWordIO, DCacheLineIO, MemoryOpConstants} 28import xiangshan.cache.mmu.{TlbRequestIO, TlbHintIO} 29import xiangshan.mem._ 30import xiangshan.backend._ 31import xiangshan.backend.rob.RobLsqIO 32 33class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 34 val isStore = Input(Bool()) 35 val vaddr = Output(UInt(VAddrBits.W)) 36} 37 38class FwdEntry extends Bundle { 39 val validFast = Bool() // validFast is generated the same cycle with query 40 val valid = Bool() // valid is generated 1 cycle after query request 41 val data = UInt(8.W) // data is generated 1 cycle after query request 42} 43 44// inflight miss block reqs 45class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 46 val block_addr = UInt(PAddrBits.W) 47 val valid = Bool() 48} 49 50class LsqEnqIO(implicit p: Parameters) extends MemBlockBundle { 51 val canAccept = Output(Bool()) 52 val needAlloc = Vec(LSQEnqWidth, Input(UInt(2.W))) 53 val req = Vec(LSQEnqWidth, Flipped(ValidIO(new DynInst))) 54 val resp = Vec(LSQEnqWidth, Output(new LSIdx)) 55} 56 57// Load / Store Queue Wrapper for XiangShan Out of Order LSU 58class LsqWrapper(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasPerfEvents { 59 val io = IO(new Bundle() { 60 val hartId = Input(UInt(8.W)) 61 val brqRedirect = Flipped(ValidIO(new Redirect)) 62 val stvecFeedback = Flipped(ValidIO(new FeedbackToLsqIO)) 63 val ldvecFeedback = Flipped(ValidIO(new FeedbackToLsqIO)) 64 val enq = new LsqEnqIO 65 val ldu = new Bundle() { 66 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 67 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 68 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 69 } 70 val sta = new Bundle() { 71 val storeMaskIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreMaskBundle))) // from store_s0, store mask, send to sq from rs 72 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 73 val storeAddrInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) // from store_s2 74 } 75 val std = new Bundle() { 76 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput(isVector = true)))) // from store_s0, store data, send to sq from rs 77 } 78 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 79 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 80 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 81 val sbuffer = Vec(EnsbufferWidth, Decoupled(new DCacheWordReqWithVaddrAndPfFlag)) 82 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 83 val rob = Flipped(new RobLsqIO) 84 val nuke_rollback = Output(Valid(new Redirect)) 85 val nack_rollback = Output(Valid(new Redirect)) 86 val release = Flipped(Valid(new Release)) 87 val refill = Flipped(Valid(new Refill)) 88 val tl_d_channel = Input(new DcacheToLduForwardIO) 89 val uncacheOutstanding = Input(Bool()) 90 val uncache = new UncacheWordIO 91 val mmioStout = DecoupledIO(new MemExuOutput) // writeback uncached store 92 // TODO: implement vector store 93 val vecmmioStout = DecoupledIO(new MemExuOutput(isVector = true)) // vec writeback uncached store 94 val sqEmpty = Output(Bool()) 95 val lq_rep_full = Output(Bool()) 96 val sqFull = Output(Bool()) 97 val lqFull = Output(Bool()) 98 val sqCancelCnt = Output(UInt(log2Up(StoreQueueSize+1).W)) 99 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 100 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 101 val sqDeq = Output(UInt(log2Ceil(EnsbufferWidth + 1).W)) 102 val lqCanAccept = Output(Bool()) 103 val sqCanAccept = Output(Bool()) 104 val lqDeqPtr = Output(new LqPtr) 105 val sqDeqPtr = Output(new SqPtr) 106 val exceptionAddr = new ExceptionAddrIO 107 val trigger = Vec(LoadPipelineWidth, new LqTriggerIO) 108 val issuePtrExt = Output(new SqPtr) 109 val l2_hint = Input(Valid(new L2ToL1Hint())) 110 val tlb_hint = Flipped(new TlbHintIO) 111 val force_write = Output(Bool()) 112 val lqEmpty = Output(Bool()) 113 114 // top-down 115 val debugTopDown = new LoadQueueTopDownIO 116 }) 117 118 val loadQueue = Module(new LoadQueue) 119 val storeQueue = Module(new StoreQueue) 120 121 storeQueue.io.hartId := io.hartId 122 storeQueue.io.uncacheOutstanding := io.uncacheOutstanding 123 124 125 dontTouch(loadQueue.io.tlbReplayDelayCycleCtrl) 126 // Todo: imm 127 val tlbReplayDelayCycleCtrl = WireInit(VecInit(Seq(14.U(ReSelectLen.W), 0.U(ReSelectLen.W), 125.U(ReSelectLen.W), 0.U(ReSelectLen.W)))) 128 loadQueue.io.tlbReplayDelayCycleCtrl := tlbReplayDelayCycleCtrl 129 130 // io.enq logic 131 // LSQ: send out canAccept when both load queue and store queue are ready 132 // Dispatch: send instructions to LSQ only when they are ready 133 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 134 io.lqCanAccept := loadQueue.io.enq.canAccept 135 io.sqCanAccept := storeQueue.io.enq.canAccept 136 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 137 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 138 io.lqDeqPtr := loadQueue.io.lqDeqPtr 139 io.sqDeqPtr := storeQueue.io.sqDeqPtr 140 for (i <- io.enq.req.indices) { 141 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 142 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 143 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 144 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 145 146 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 147 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 148 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 149 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 150 151 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 152 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 153 } 154 155 // store queue wiring 156 storeQueue.io.brqRedirect <> io.brqRedirect 157 storeQueue.io.vecFeedback <> io.stvecFeedback 158 storeQueue.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 159 storeQueue.io.storeAddrInRe <> io.sta.storeAddrInRe // from store_s2 160 storeQueue.io.storeDataIn <> io.std.storeDataIn // from store_s0 161 storeQueue.io.storeMaskIn <> io.sta.storeMaskIn // from store_s0 162 storeQueue.io.sbuffer <> io.sbuffer 163 storeQueue.io.mmioStout <> io.mmioStout 164 storeQueue.io.vecmmioStout <> io.vecmmioStout 165 storeQueue.io.rob <> io.rob 166 storeQueue.io.exceptionAddr.isStore := DontCare 167 storeQueue.io.sqCancelCnt <> io.sqCancelCnt 168 storeQueue.io.sqDeq <> io.sqDeq 169 storeQueue.io.sqEmpty <> io.sqEmpty 170 storeQueue.io.sqFull <> io.sqFull 171 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 172 storeQueue.io.force_write <> io.force_write 173 174 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 175 176 // load queue wiring 177 loadQueue.io.redirect <> io.brqRedirect 178 loadQueue.io.vecFeedback <> io.ldvecFeedback 179 loadQueue.io.ldu <> io.ldu 180 loadQueue.io.ldout <> io.ldout 181 loadQueue.io.ld_raw_data <> io.ld_raw_data 182 loadQueue.io.rob <> io.rob 183 loadQueue.io.nuke_rollback <> io.nuke_rollback 184 loadQueue.io.nack_rollback <> io.nack_rollback 185 loadQueue.io.replay <> io.replay 186 loadQueue.io.refill <> io.refill 187 loadQueue.io.tl_d_channel <> io.tl_d_channel 188 loadQueue.io.release <> io.release 189 loadQueue.io.trigger <> io.trigger 190 loadQueue.io.exceptionAddr.isStore := DontCare 191 loadQueue.io.lqCancelCnt <> io.lqCancelCnt 192 loadQueue.io.sq.stAddrReadySqPtr <> storeQueue.io.stAddrReadySqPtr 193 loadQueue.io.sq.stAddrReadyVec <> storeQueue.io.stAddrReadyVec 194 loadQueue.io.sq.stDataReadySqPtr <> storeQueue.io.stDataReadySqPtr 195 loadQueue.io.sq.stDataReadyVec <> storeQueue.io.stDataReadyVec 196 loadQueue.io.sq.stIssuePtr <> storeQueue.io.stIssuePtr 197 loadQueue.io.sq.sqEmpty <> storeQueue.io.sqEmpty 198 loadQueue.io.sta.storeAddrIn <> io.sta.storeAddrIn // store_s1 199 loadQueue.io.std.storeDataIn <> io.std.storeDataIn // store_s0 200 loadQueue.io.lqFull <> io.lqFull 201 loadQueue.io.lq_rep_full <> io.lq_rep_full 202 loadQueue.io.lqDeq <> io.lqDeq 203 loadQueue.io.l2_hint <> io.l2_hint 204 loadQueue.io.tlb_hint <> io.tlb_hint 205 loadQueue.io.lqEmpty <> io.lqEmpty 206 207 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 208 // s0: commit 209 // s1: exception find 210 // s2: exception triggered 211 // s3: ptr updated & new address 212 // address will be used at the next cycle after exception is triggered 213 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 214 io.issuePtrExt := storeQueue.io.stAddrReadySqPtr 215 216 // naive uncache arbiter 217 val s_idle :: s_load :: s_store :: Nil = Enum(3) 218 val pendingstate = RegInit(s_idle) 219 220 switch(pendingstate){ 221 is(s_idle){ 222 when(io.uncache.req.fire){ 223 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, 224 Mux(io.uncacheOutstanding, s_idle, s_store)) 225 } 226 } 227 is(s_load){ 228 when(io.uncache.resp.fire){ 229 pendingstate := s_idle 230 } 231 } 232 is(s_store){ 233 when(io.uncache.resp.fire){ 234 pendingstate := s_idle 235 } 236 } 237 } 238 239 loadQueue.io.uncache := DontCare 240 storeQueue.io.uncache := DontCare 241 loadQueue.io.uncache.req.ready := false.B 242 storeQueue.io.uncache.req.ready := false.B 243 loadQueue.io.uncache.resp.valid := false.B 244 storeQueue.io.uncache.resp.valid := false.B 245 when(loadQueue.io.uncache.req.valid){ 246 io.uncache.req <> loadQueue.io.uncache.req 247 }.otherwise{ 248 io.uncache.req <> storeQueue.io.uncache.req 249 } 250 when (io.uncacheOutstanding) { 251 io.uncache.resp <> loadQueue.io.uncache.resp 252 } .otherwise { 253 when(pendingstate === s_load){ 254 io.uncache.resp <> loadQueue.io.uncache.resp 255 }.otherwise{ 256 io.uncache.resp <> storeQueue.io.uncache.resp 257 } 258 } 259 260 loadQueue.io.debugTopDown <> io.debugTopDown 261 262 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 263 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 264 when (!io.uncacheOutstanding) { 265 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 266 } 267 268 269 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) 270 generatePerfEvent() 271} 272 273class LsqEnqCtrl(implicit p: Parameters) extends XSModule 274 with HasVLSUParameters { 275 val io = IO(new Bundle { 276 val redirect = Flipped(ValidIO(new Redirect)) 277 // to dispatch 278 val enq = new LsqEnqIO 279 // from `memBlock.io.lqDeq 280 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 281 // from `memBlock.io.sqDeq` 282 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 283 // from/tp lsq 284 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 285 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 286 val lqFreeCount = Output(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 287 val sqFreeCount = Output(UInt(log2Up(StoreQueueSize + 1).W)) 288 val enqLsq = Flipped(new LsqEnqIO) 289 }) 290 291 val lqPtr = RegInit(0.U.asTypeOf(new LqPtr)) 292 val sqPtr = RegInit(0.U.asTypeOf(new SqPtr)) 293 val lqCounter = RegInit(VirtualLoadQueueSize.U(log2Up(VirtualLoadQueueSize + 1).W)) 294 val sqCounter = RegInit(StoreQueueSize.U(log2Up(StoreQueueSize + 1).W)) 295 val canAccept = RegInit(false.B) 296 297 val loadEnqVec = io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(0)) 298 val storeEnqVec = io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(1)) 299 val isLastUopVec = io.enq.req.map(_.bits.lastUop) 300 val vLoadFlow = io.enq.req.map(_.bits.numLsElem) 301 val vStoreFlow = io.enq.req.map(_.bits.numLsElem) 302 val validVLoadFlow = vLoadFlow.zipWithIndex.map{case (vLoadFlowNum_Item, index) => Mux(loadEnqVec(index), vLoadFlowNum_Item, 0.U)} 303 val validVStoreFlow = vStoreFlow.zipWithIndex.map{case (vStoreFlowNum_Item, index) => Mux(storeEnqVec(index), vStoreFlowNum_Item, 0.U)} 304 val enqVLoadOffsetNumber = validVLoadFlow.reduce(_ + _) 305 val enqVStoreOffsetNumber = validVStoreFlow.reduce(_ + _) 306 val validVLoadOffset = 0.U +: vLoadFlow.zip(io.enq.needAlloc) 307 .map{case (flow, needAlloc_Item) => Mux(needAlloc_Item(0).asBool, flow, 0.U)} 308 .slice(0, validVLoadFlow.length - 1) 309 val validVStoreOffset = 0.U +: vStoreFlow.zip(io.enq.needAlloc) 310 .map{case (flow, needAlloc_Item) => Mux(needAlloc_Item(1).asBool, flow, 0.U)} 311 .slice(0, validVStoreFlow.length - 1) 312 val lqAllocNumber = enqVLoadOffsetNumber 313 val sqAllocNumber = enqVStoreOffsetNumber 314 315 io.lqFreeCount := lqCounter 316 io.sqFreeCount := sqCounter 317 // How to update ptr and counter: 318 // (1) by default, updated according to enq/commit 319 // (2) when redirect and dispatch queue is empty, update according to lsq 320 val t1_redirect = RegNext(io.redirect.valid) 321 val t2_redirect = RegNext(t1_redirect) 322 val t2_update = t2_redirect && !VecInit(io.enq.needAlloc.map(_.orR)).asUInt.orR 323 val t3_update = RegNext(t2_update) 324 val t3_lqCancelCnt = RegNext(io.lqCancelCnt) 325 val t3_sqCancelCnt = RegNext(io.sqCancelCnt) 326 when (t3_update) { 327 lqPtr := lqPtr - t3_lqCancelCnt 328 lqCounter := lqCounter + io.lcommit + t3_lqCancelCnt 329 sqPtr := sqPtr - t3_sqCancelCnt 330 sqCounter := sqCounter + io.scommit + t3_sqCancelCnt 331 }.elsewhen (!io.redirect.valid && io.enq.canAccept) { 332 lqPtr := lqPtr + lqAllocNumber 333 lqCounter := lqCounter + io.lcommit - lqAllocNumber 334 sqPtr := sqPtr + sqAllocNumber 335 sqCounter := sqCounter + io.scommit - sqAllocNumber 336 }.otherwise { 337 lqCounter := lqCounter + io.lcommit 338 sqCounter := sqCounter + io.scommit 339 } 340 341 342 val lqMaxAllocate = LSQLdEnqWidth 343 val sqMaxAllocate = LSQStEnqWidth 344 val maxAllocate = lqMaxAllocate max sqMaxAllocate 345 val ldCanAccept = lqCounter >= lqAllocNumber +& lqMaxAllocate.U 346 val sqCanAccept = sqCounter >= sqAllocNumber +& sqMaxAllocate.U 347 // It is possible that t3_update and enq are true at the same clock cycle. 348 // For example, if redirect.valid lasts more than one clock cycle, 349 // after the last redirect, new instructions may enter but previously redirect has not been resolved (updated according to the cancel count from LSQ). 350 // To solve the issue easily, we block enqueue when t3_update, which is RegNext(t2_update). 351 io.enq.canAccept := RegNext(ldCanAccept && sqCanAccept && !t2_update) 352 val lqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 353 val sqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 354 for ((resp, i) <- io.enq.resp.zipWithIndex) { 355 lqOffset(i) := validVLoadOffset.take(i + 1).reduce(_ + _) 356 resp.lqIdx := lqPtr + lqOffset(i) 357 sqOffset(i) := validVStoreOffset.take(i + 1).reduce(_ + _) 358 resp.sqIdx := sqPtr + sqOffset(i) 359 } 360 361 io.enqLsq.needAlloc := RegNext(io.enq.needAlloc) 362 io.enqLsq.req.zip(io.enq.req).zip(io.enq.resp).foreach{ case ((toLsq, enq), resp) => 363 val do_enq = enq.valid && !io.redirect.valid && io.enq.canAccept 364 toLsq.valid := RegNext(do_enq) 365 toLsq.bits := RegEnable(enq.bits, do_enq) 366 toLsq.bits.lqIdx := RegEnable(resp.lqIdx, do_enq) 367 toLsq.bits.sqIdx := RegEnable(resp.sqIdx, do_enq) 368 } 369 370}