1package xiangshan.backend.datapath 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DiffArchFpRegState, DiffArchIntRegState, DiffArchVecRegState, DifftestModule} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import utils.SeqUtils._ 10import xiangshan._ 11import xiangshan.backend.BackendParams 12import xiangshan.backend.Bundles._ 13import xiangshan.backend.decode.ImmUnion 14import xiangshan.backend.datapath.DataConfig._ 15import xiangshan.backend.datapath.RdConfig._ 16import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 17import xiangshan.backend.implicitCast._ 18import xiangshan.backend.regfile._ 19 20class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 21 private implicit val dpParams: BackendParams = params 22 lazy val module = new DataPathImp(this) 23 24 println(s"[DataPath] Preg Params: ") 25 println(s"[DataPath] Int R(${params.getRfReadSize(IntData())}), W(${params.getRfWriteSize(IntData())}) ") 26 println(s"[DataPath] Vf R(${params.getRfReadSize(VecData())}), W(${params.getRfWriteSize(VecData())}) ") 27} 28 29class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 30 extends LazyModuleImp(wrapper) with HasXSParameter { 31 32 private val VCONFIG_PORT = params.vconfigPort 33 34 val io = IO(new DataPathIO()) 35 36 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 37 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 38 private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toFpExu) 39 40 println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromMemIQ.size})") 41 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 42 43 // just refences for convience 44 private val fromIQ: Seq[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = fromIntIQ ++ fromVfIQ ++ fromMemIQ 45 46 private val toIQs = toIntIQ ++ toVfIQ ++ toMemIQ 47 48 private val toExu: Seq[MixedVec[DecoupledIO[ExuInput]]] = toIntExu ++ toVfExu ++ toMemExu 49 50 private val fromFlattenIQ: Seq[DecoupledIO[IssueQueueIssueBundle]] = fromIQ.flatten 51 52 private val toFlattenExu: Seq[DecoupledIO[ExuInput]] = toExu.flatten 53 54 private val intWbBusyArbiter = Module(new IntRFWBCollideChecker(backendParams)) 55 private val vfWbBusyArbiter = Module(new VfRFWBCollideChecker(backendParams)) 56 private val intRFReadArbiter = Module(new IntRFReadArbiter(backendParams)) 57 private val vfRFReadArbiter = Module(new VfRFReadArbiter(backendParams)) 58 59 private val og0FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 60 private val og1FailedVec2: MixedVec[Vec[Bool]] = Wire(MixedVec(fromIQ.map(x => Vec(x.size, Bool())).toSeq)) 61 62 // port -> win 63 private val intRdArbWinner: Seq2[MixedVec[Bool]] = intRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 64 private val vfRdArbWinner: Seq2[MixedVec[Bool]] = vfRFReadArbiter.io.in.map(_.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq).toSeq 65 private val intWbNotBlock: Seq[MixedVec[Bool]] = intWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 66 private val vfWbNotBlock: Seq[MixedVec[Bool]] = vfWbBusyArbiter.io.in.map(x => MixedVecInit(x.map(_.ready).toSeq)).toSeq 67 68 private val intRdNotBlock: Seq2[Bool] = intRdArbWinner.map(_.map(_.asUInt.andR)) 69 private val vfRdNotBlock: Seq2[Bool] = vfRdArbWinner.map(_.map(_.asUInt.andR)) 70 71 private val intRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getIntRfReadValidBundle(xx.valid)).toSeq).toSeq 72 73 intRFReadArbiter.io.in.zip(intRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 74 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 75 val srcIndices: Seq[Int] = fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(IntData()) 76 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 77 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 78 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid 79 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 80 } else { 81 arbInSeq(srcIdx).valid := false.B 82 arbInSeq(srcIdx).bits.addr := 0.U 83 } 84 } 85 } 86 } 87 88 private val vfRFReadReq: Seq3[ValidIO[RfReadPortWithConfig]] = fromIQ.map(x => x.map(xx => xx.bits.getVfRfReadValidBundle(xx.valid)).toSeq).toSeq 89 90 vfRFReadArbiter.io.in.zip(vfRFReadReq).zipWithIndex.foreach { case ((arbInSeq2, inRFReadReqSeq2), iqIdx) => 91 arbInSeq2.zip(inRFReadReqSeq2).zipWithIndex.foreach { case ((arbInSeq, inRFReadReqSeq), exuIdx) => 92 val srcIndices: Seq[Int] = VfRegSrcDataSet.flatMap(data => fromIQ(iqIdx)(exuIdx).bits.exuParams.getRfReadSrcIdx(data)).toSeq.sorted 93 for (srcIdx <- 0 until fromIQ(iqIdx)(exuIdx).bits.exuParams.numRegSrc) { 94 if (srcIndices.contains(srcIdx) && inRFReadReqSeq.isDefinedAt(srcIdx)) { 95 arbInSeq(srcIdx).valid := inRFReadReqSeq(srcIdx).valid 96 arbInSeq(srcIdx).bits.addr := inRFReadReqSeq(srcIdx).bits.addr 97 } else { 98 arbInSeq(srcIdx).valid := false.B 99 arbInSeq(srcIdx).bits.addr := 0.U 100 } 101 } 102 } 103 } 104 105 private val intRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.rfWen.getOrElse(false.B)).toSeq).toSeq 106 private val vfRFWriteReq: Seq2[Bool] = fromIQ.map(x => x.map(xx => xx.valid && xx.bits.common.getVfWen.getOrElse(false.B)).toSeq).toSeq 107 108 intWbBusyArbiter.io.in.zip(intRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 109 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 110 arbIn.valid := inRFWriteReq 111 } 112 } 113 114 vfWbBusyArbiter.io.in.zip(vfRFWriteReq).foreach { case (arbInSeq, inRFWriteReqSeq) => 115 arbInSeq.zip(inRFWriteReqSeq).foreach { case (arbIn, inRFWriteReq) => 116 arbIn.valid := inRFWriteReq 117 } 118 } 119 120 private val intSchdParams = params.schdParams(IntScheduler()) 121 private val vfSchdParams = params.schdParams(VfScheduler()) 122 private val memSchdParams = params.schdParams(MemScheduler()) 123 124 private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu 125 private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu 126 // Todo: limit read port 127 private val numIntR = numIntRfReadByExu 128 private val numVfR = numVfRfReadByExu 129 println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Vf(${numVfRfReadByExu})") 130 println(s"[DataPath] RegFile read port: Int(${numIntR}), Vf(${numVfR})") 131 132 private val schdParams = params.allSchdParams 133 134 private val intRfRaddr = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.pregIdxWidth.W))) 135 private val intRfRdata = Wire(Vec(params.numPregRd(IntData()), UInt(intSchdParams.rfDataWidth.W))) 136 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 137 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 138 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 139 140 private val vfRfSplitNum = VLEN / XLEN 141 private val vfRfRaddr = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.pregIdxWidth.W))) 142 private val vfRfRdata = Wire(Vec(params.numPregRd(VecData()), UInt(vfSchdParams.rfDataWidth.W))) 143 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 144 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 145 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 146 147 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 148 if (env.AlwaysBasicDiff || env.EnableDifftest) { 149 Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 150 } else { None } 151 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 152 if (env.AlwaysBasicDiff || env.EnableDifftest) { 153 Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W)))) 154 } else { None } 155 156 private val fpDebugReadData: Option[Vec[UInt]] = 157 if (env.AlwaysBasicDiff || env.EnableDifftest) { 158 Some(Wire(Vec(32, UInt(XLEN.W)))) 159 } else { None } 160 private val vecDebugReadData: Option[Vec[UInt]] = 161 if (env.AlwaysBasicDiff || env.EnableDifftest) { 162 Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 163 } else { None } 164 private val vconfigDebugReadData: Option[UInt] = 165 if (env.AlwaysBasicDiff || env.EnableDifftest) { 166 Some(Wire(UInt(64.W))) 167 } else { None } 168 169 170 fpDebugReadData.foreach(_ := vfDebugRead 171 .get._2 172 .slice(0, 32) 173 .map(_(63, 0)) 174 ) // fp only used [63, 0] 175 vecDebugReadData.foreach(_ := vfDebugRead 176 .get._2 177 .slice(32, 64) 178 .map(x => Seq(x(63, 0), x(127, 64))).flatten 179 ) 180 vconfigDebugReadData.foreach(_ := vfDebugRead 181 .get._2(64)(63, 0) 182 ) 183 184 io.debugVconfig.foreach(_ := vconfigDebugReadData.get) 185 186 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 187 debugReadAddr = intDebugRead.map(_._1), 188 debugReadData = intDebugRead.map(_._2)) 189 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 190 debugReadAddr = vfDebugRead.map(_._1), 191 debugReadData = vfDebugRead.map(_._2)) 192 193 intRfWaddr := io.fromIntWb.map(_.addr).toSeq 194 intRfWdata := io.fromIntWb.map(_.data).toSeq 195 intRfWen := io.fromIntWb.map(_.wen).toSeq 196 197 for (portIdx <- intRfRaddr.indices) { 198 if (intRFReadArbiter.io.out.isDefinedAt(portIdx)) 199 intRfRaddr(portIdx) := intRFReadArbiter.io.out(portIdx).bits.addr 200 else 201 intRfRaddr(portIdx) := 0.U 202 } 203 204 vfRfWaddr := io.fromVfWb.map(_.addr).toSeq 205 vfRfWdata := io.fromVfWb.map(_.data).toSeq 206 vfRfWen.foreach(_.zip(io.fromVfWb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write 207 208 for (portIdx <- vfRfRaddr.indices) { 209 if (vfRFReadArbiter.io.out.isDefinedAt(portIdx)) 210 vfRfRaddr(portIdx) := vfRFReadArbiter.io.out(portIdx).bits.addr 211 else 212 vfRfRaddr(portIdx) := 0.U 213 } 214 215 vfRfRaddr(VCONFIG_PORT) := io.vconfigReadPort.addr 216 io.vconfigReadPort.data := vfRfRdata(VCONFIG_PORT) 217 218 intDebugRead.foreach { case (addr, _) => 219 addr := io.debugIntRat.get 220 } 221 222 vfDebugRead.foreach { case (addr, _) => 223 addr := io.debugFpRat.get ++ io.debugVecRat.get :+ io.debugVconfigRat.get 224 } 225 println(s"[DataPath] " + 226 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 227 s"has vfDebugRead: ${vfDebugRead.nonEmpty}") 228 229 val s1_addrOHs = Reg(MixedVec( 230 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType).toSeq)).toSeq 231 )) 232 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 233 toExu.map(x => MixedVec(x.map(_.valid.cloneType).toSeq)).toSeq 234 )) 235 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType).toSeq)).toSeq)) 236 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType))))) // Todo 237 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire))))) 238 239 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 240 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 241 242 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 243 244 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 245 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 246 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 247 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 248 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten 249 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 250 iuRdata.zip(realIuCfg) 251 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 252 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 253 } 254 } 255 256 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 257 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 258 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 259 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 260 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten 261 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 262 iuRdata.zip(realIuCfg) 263 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 264 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 265 } 266 } 267 268 for (i <- fromIQ.indices) { 269 for (j <- fromIQ(i).indices) { 270 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 271 // refs 272 val s1_valid = s1_toExuValid(i)(j) 273 val s1_ready = s1_toExuReady(i)(j) 274 val s1_data = s1_toExuData(i)(j) 275 val s1_addrOH = s1_addrOHs(i)(j) 276 val s0 = fromIQ(i)(j) // s0 277 val notBlock = intRdNotBlock(i)(j) && intWbNotBlock(i)(j) && vfRdNotBlock(i)(j) && vfWbNotBlock(i)(j) 278 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 279 val s1_cancel = og1FailedVec2(i)(j) 280 val s1_ldCancel = LoadShouldCancel(s0.bits.common.loadDependency, io.ldCancel) 281 when (s0.fire && !s1_flush && notBlock && !s1_cancel && !s1_ldCancel) { 282 s1_valid := s0.valid 283 s1_data.fromIssueBundle(s0.bits) // no src data here 284 s1_addrOH := s0.bits.addrOH 285 }.otherwise { 286 s1_valid := false.B 287 } 288 s0.ready := (s1_ready || !s1_valid) && notBlock 289 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 290 291 // IQ(s0) --[Data]--> s1Reg ---------- begin 292 // imm extract 293 when (s0.fire && !s1_flush && notBlock) { 294 if (s1_data.params.immType.nonEmpty && s1_data.src.size > 1) { 295 // rs1 is always int reg, rs2 may be imm 296 when(SrcType.isImm(s0.bits.srcType(1))) { 297 s1_data.src(1) := ImmExtractor( 298 s0.bits.common.imm, 299 s0.bits.immType, 300 s1_data.params.dataBitsMax, 301 s1_data.params.immType.map(_.litValue) 302 ) 303 } 304 } 305 if (s1_data.params.hasJmpFu) { 306 when(SrcType.isPc(s0.bits.srcType(0))) { 307 s1_data.src(0) := SignExt(s0.bits.common.pc.get, XLEN) 308 } 309 } else if (s1_data.params.hasVecFu) { 310 // Fuck off riscv vector imm!!! Why not src1??? 311 when(SrcType.isImm(s0.bits.srcType(0))) { 312 s1_data.src(0) := ImmExtractor( 313 s0.bits.common.imm, 314 s0.bits.immType, 315 s1_data.params.dataBitsMax, 316 s1_data.params.immType.map(_.litValue) 317 ) 318 } 319 } else if (s1_data.params.hasLoadFu) { 320 // dirty code for fused_lui_load 321 when(SrcType.isImm(s0.bits.srcType(0))) { 322 s1_data.src(0) := SignExt(ImmUnion.U.toImm32(s0.bits.common.imm(s0.bits.common.imm.getWidth - 1, ImmUnion.I.len)), XLEN) 323 } 324 } 325 } 326 // IQ(s0) --[Data]--> s1Reg ---------- end 327 } 328 } 329 330 private val fromIQFire = fromIQ.map(_.map(_.fire)) 331 private val toExuFire = toExu.map(_.map(_.fire)) 332 toIQs.zipWithIndex.foreach { 333 case(toIQ, iqIdx) => 334 toIQ.zipWithIndex.foreach { 335 case (toIU, iuIdx) => 336 // IU: issue unit 337 val og0resp = toIU.og0resp 338 og0FailedVec2(iqIdx)(iuIdx) := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 339 og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) 340 og0resp.bits.respType := RSFeedbackType.rfArbitFail 341 og0resp.bits.dataInvalidSqIdx := DontCare 342 og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx 343 og0resp.bits.rfWen := fromIQ(iqIdx)(iuIdx).bits.common.rfWen.getOrElse(false.B) 344 og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType 345 346 val og1resp = toIU.og1resp 347 og1FailedVec2(iqIdx)(iuIdx) := s1_toExuValid(iqIdx)(iuIdx) && !toExuFire(iqIdx)(iuIdx) 348 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 349 og1resp.bits.respType := Mux(!og1FailedVec2(iqIdx)(iuIdx), 350 if (toIU.issueQueueParams.isMemAddrIQ) RSFeedbackType.fuUncertain else RSFeedbackType.fuIdle, 351 RSFeedbackType.fuBusy) 352 og1resp.bits.dataInvalidSqIdx := DontCare 353 og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx 354 og1resp.bits.rfWen := s1_toExuData(iqIdx)(iuIdx).rfWen.getOrElse(false.B) 355 og1resp.bits.fuType := s1_toExuData(iqIdx)(iuIdx).fuType 356 } 357 } 358 359 io.og0CancelVec.zip(io.og1CancelVec).zipWithIndex.foreach { case ((og0Cancel, og1Cancel), i) => 360 og0Cancel := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire 361 og1Cancel := toFlattenExu(i).valid && !toFlattenExu(i).fire 362 } 363 364 io.cancelToBusyTable.zipWithIndex.foreach { case (cancel, i) => 365 cancel.valid := fromFlattenIQ(i).valid && !fromFlattenIQ(i).fire && { 366 if (fromFlattenIQ(i).bits.common.rfWen.isDefined) 367 fromFlattenIQ(i).bits.common.rfWen.get && fromFlattenIQ(i).bits.common.pdest =/= 0.U 368 else 369 true.B 370 } 371 cancel.bits.rfWen := fromFlattenIQ(i).bits.common.rfWen.getOrElse(false.B) 372 cancel.bits.fpWen := fromFlattenIQ(i).bits.common.fpWen.getOrElse(false.B) 373 cancel.bits.vecWen := fromFlattenIQ(i).bits.common.vecWen.getOrElse(false.B) 374 cancel.bits.pdest := fromFlattenIQ(i).bits.common.pdest 375 } 376 377 for (i <- toExu.indices) { 378 for (j <- toExu(i).indices) { 379 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 380 // refs 381 val sinkData = toExu(i)(j).bits 382 // assign 383 toExu(i)(j).valid := s1_toExuValid(i)(j) 384 s1_toExuReady(i)(j) := toExu(i)(j).ready 385 sinkData := s1_toExuData(i)(j) 386 // s1Reg --[Ctrl]--> exu(s1) ---------- end 387 388 // s1Reg --[Data]--> exu(s1) ---------- begin 389 // data source1: preg read data 390 for (k <- sinkData.src.indices) { 391 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 392 393 val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+ 394 (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty) 395 Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k)) 396 else None) :+ 397 (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty) 398 Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k)) 399 else None) 400 ).filter(_.nonEmpty).map(_.get) 401 if (readRfMap.nonEmpty) 402 sinkData.src(k) := Mux1H(readRfMap) 403 } 404 405 // data source2: extracted imm and pc saved in s1Reg 406 if (sinkData.params.immType.nonEmpty && sinkData.src.size > 1) { 407 when(SrcType.isImm(s1_srcType(i)(j)(1))) { 408 sinkData.src(1) := s1_toExuData(i)(j).src(1) 409 } 410 } 411 if (sinkData.params.hasJmpFu) { 412 when(SrcType.isPc(s1_srcType(i)(j)(0))) { 413 sinkData.src(0) := s1_toExuData(i)(j).src(0) 414 } 415 } else if (sinkData.params.hasVecFu) { 416 when(SrcType.isImm(s1_srcType(i)(j)(0))) { 417 sinkData.src(0) := s1_toExuData(i)(j).src(0) 418 } 419 } else if (sinkData.params.hasLoadFu) { 420 when(SrcType.isImm(s1_srcType(i)(j)(0))) { 421 sinkData.src(0) := s1_toExuData(i)(j).src(0) 422 } 423 } 424 // s1Reg --[Data]--> exu(s1) ---------- end 425 } 426 } 427 428 if (env.AlwaysBasicDiff || env.EnableDifftest) { 429 val delayedCnt = 2 430 val difftestArchIntRegState = DifftestModule(new DiffArchIntRegState, delay = delayedCnt) 431 difftestArchIntRegState.coreid := io.hartId 432 difftestArchIntRegState.value := intDebugRead.get._2 433 434 val difftestArchFpRegState = DifftestModule(new DiffArchFpRegState, delay = delayedCnt) 435 difftestArchFpRegState.coreid := io.hartId 436 difftestArchFpRegState.value := fpDebugReadData.get 437 438 val difftestArchVecRegState = DifftestModule(new DiffArchVecRegState, delay = delayedCnt) 439 difftestArchVecRegState.coreid := io.hartId 440 difftestArchVecRegState.value := vecDebugReadData.get 441 } 442} 443 444class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 445 // params 446 private val intSchdParams = params.schdParams(IntScheduler()) 447 private val vfSchdParams = params.schdParams(VfScheduler()) 448 private val memSchdParams = params.schdParams(MemScheduler()) 449 private val exuParams = params.allExuParams 450 // bundles 451 val hartId = Input(UInt(8.W)) 452 453 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 454 455 // Todo: check if this can be removed 456 val vconfigReadPort = new RfReadPort(XLEN, PhyRegIdxWidth) 457 458 val wbConfictRead = Input(MixedVec(params.allSchdParams.map(x => MixedVec(x.issueBlockParams.map(x => x.genWbConflictBundle()))))) 459 460 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 461 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 462 463 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 464 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 465 466 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 467 468 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 469 470 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 471 472 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 473 474 val og0CancelVec = Output(ExuVec(backendParams.numExu)) 475 476 val og1CancelVec = Output(ExuVec(backendParams.numExu)) 477 478 val ldCancel = Vec(backendParams.LduCnt, Flipped(new LoadCancelIO)) 479 480 val cancelToBusyTable = Vec(backendParams.numExu, ValidIO(new CancelSignal)) 481 482 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 483 484 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 485 486 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 487 488 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 489 490 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 491 492 val debugIntRat = if (params.debugEn) Some(Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W)))) else None 493 val debugFpRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 494 val debugVecRat = if (params.debugEn) Some(Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W)))) else None 495 val debugVconfigRat = if (params.debugEn) Some(Input(UInt(vfSchdParams.pregIdxWidth.W))) else None 496 val debugVconfig = if (params.debugEn) Some(Output(UInt(XLEN.W))) else None 497} 498