1// /*************************************************************************************** 2// * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3// * 4// * XiangShan is licensed under Mulan PSL v2. 5// * You can use this software according to the terms and conditions of the Mulan PSL v2. 6// * You may obtain a copy of Mulan PSL v2 at: 7// * http://license.coscl.org.cn/MulanPSL2 8// * 9// * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10// * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11// * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12// * 13// * See the Mulan PSL v2 for more details. 14// ***************************************************************************************/ 15 16// package xiangshan.frontend 17 18// import chipsalliance.rocketchip.config.Parameters 19// import chisel3._ 20// import chisel3.util._ 21// import xiangshan._ 22// import utils._ 23// import xiangshan.cache._ 24// import chisel3.experimental.chiselName 25// import freechips.rocketchip.tile.HasLazyRoCC 26// import system.L1CacheErrorInfo 27 28// trait HasInstrMMIOConst extends HasXSParameter with HasIFUConst{ 29// def mmioBusWidth = 64 30// def mmioBusBytes = mmioBusWidth /8 31// def mmioBeats = FetchWidth * 4 * 8 / mmioBusWidth 32// def mmioMask = VecInit(List.fill(PredictWidth)(true.B)).asUInt 33// def mmioBusAligned(pc :UInt): UInt = align(pc, mmioBusBytes) 34// } 35 36// trait HasIFUConst extends HasXSParameter { 37// val resetVector = 0x10000000L//TODO: set reset vec 38// def align(pc: UInt, bytes: Int): UInt = Cat(pc(VAddrBits-1, log2Ceil(bytes)), 0.U(log2Ceil(bytes).W)) 39// val groupBytes = 64 // correspond to cache line size 40// val groupOffsetBits = log2Ceil(groupBytes) 41// val groupWidth = groupBytes / instBytes 42// val packetBytes = PredictWidth * instBytes 43// val packetOffsetBits = log2Ceil(packetBytes) 44// def offsetInPacket(pc: UInt) = pc(packetOffsetBits-1, instOffsetBits) 45// def packetIdx(pc: UInt) = pc(VAddrBits-1, log2Ceil(packetBytes)) 46// def groupAligned(pc: UInt) = align(pc, groupBytes) 47// def packetAligned(pc: UInt) = align(pc, packetBytes) 48// def mask(pc: UInt): UInt = ((~(0.U(PredictWidth.W))) << offsetInPacket(pc))(PredictWidth-1,0) 49// def snpc(pc: UInt): UInt = packetAligned(pc) + packetBytes.U 50 51// val enableGhistRepair = true 52// val IFUDebug = true 53// } 54 55// class GlobalHistory(implicit p: Parameters) extends XSBundle { 56// val predHist = UInt(HistoryLength.W) 57// def update(sawNTBr: Bool, takenOnBr: Bool, hist: UInt = predHist): GlobalHistory = { 58// val g = Wire(new GlobalHistory) 59// val shifted = takenOnBr || sawNTBr 60// g.predHist := Mux(shifted, (hist << 1) | takenOnBr.asUInt, hist) 61// g 62// } 63 64// final def === (that: GlobalHistory): Bool = { 65// predHist === that.predHist 66// } 67 68// final def =/= (that: GlobalHistory): Bool = !(this === that) 69 70// implicit val name = "IFU" 71// def debug(where: String) = XSDebug(p"[${where}_GlobalHistory] hist=${Binary(predHist)}\n") 72// // override def toString(): String = "histPtr=%d, sawNTBr=%d, takenOnBr=%d, saveHalfRVI=%d".format(histPtr, sawNTBr, takenOnBr, saveHalfRVI) 73// } 74 75 76// class IFUIO(implicit p: Parameters) extends XSBundle 77// { 78// // to ibuffer 79// val fetchPacket = DecoupledIO(new FetchPacket) 80// // from backend 81// val redirect = Flipped(ValidIO(new Redirect)) 82// val bp_ctrl = Input(new BPUCtrl) 83// val commitUpdate = Flipped(ValidIO(new FtqEntry)) 84// val ftqEnqPtr = Input(new FtqPtr) 85// val ftqLeftOne = Input(Bool()) 86// // to backend 87// val toFtq = DecoupledIO(new FtqEntry) 88// // to icache 89// val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 90// val fencei = Input(Bool()) 91// // from icache 92// val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 93// val l1plusFlush = Output(Bool()) 94// val prefetchTrainReq = ValidIO(new IcacheMissReq) 95// val error = new L1CacheErrorInfo 96// // to tlb 97// val sfence = Input(new SfenceBundle) 98// val tlbCsr = Input(new TlbCsrBundle) 99// // from tlb 100// val ptw = new TlbPtwIO 101// // icache uncache 102// val mmio_acquire = DecoupledIO(new InsUncacheReq) 103// val mmio_grant = Flipped(DecoupledIO(new InsUncacheResp)) 104// val mmio_flush = Output(Bool()) 105// } 106 107// class PrevHalfInstr(implicit p: Parameters) extends XSBundle { 108// val pc = UInt(VAddrBits.W) 109// val npc = UInt(VAddrBits.W) 110// val instr = UInt(16.W) 111// val ipf = Bool() 112// } 113 114// @chiselName 115// class IFU(implicit p: Parameters) extends XSModule with HasIFUConst with HasCircularQueuePtrHelper 116// { 117// val io = IO(new IFUIO) 118// val bpu = BPU(EnableBPU) 119// val icache = Module(new ICache) 120 121// io.ptw <> TLB( 122// in = Seq(icache.io.tlb), 123// sfence = io.sfence, 124// csr = io.tlbCsr, 125// width = 1, 126// isDtlb = false, 127// shouldBlock = true 128// ) 129 130// val if2_redirect, if3_redirect, if4_redirect = WireInit(false.B) 131// val if1_flush, if2_flush, if3_flush, if4_flush = WireInit(false.B) 132 133// val icacheResp = icache.io.resp.bits 134 135// if4_flush := io.redirect.valid 136// if3_flush := if4_flush || if4_redirect 137// if2_flush := if3_flush || if3_redirect 138// if1_flush := if2_flush || if2_redirect 139 140// //********************** IF1 ****************************// 141// val if1_valid = !reset.asBool && GTimer() > 500.U 142// val if1_npc = WireInit(0.U(VAddrBits.W)) 143// val if2_ready = WireInit(false.B) 144// val if2_valid = RegInit(init = false.B) 145// val if2_allReady = WireInit(if2_ready && icache.io.req.ready && bpu.io.in_ready) 146// val if1_fire = if1_valid && if2_allReady 147 148// val if1_gh, if2_gh, if3_gh, if4_gh = Wire(new GlobalHistory) 149// val if2_predicted_gh, if3_predicted_gh, if4_predicted_gh = Wire(new GlobalHistory) 150// val final_gh = RegInit(0.U.asTypeOf(new GlobalHistory)) 151 152// //********************** IF2 ****************************// 153// val if2_allValid = if2_valid && icache.io.tlb.resp.valid 154// val if3_ready = WireInit(false.B) 155// val if2_fire = if2_allValid && if3_ready 156// val if2_pc = RegEnable(next = if1_npc, init = resetVector.U, enable = if1_fire) 157// val if2_snpc = snpc(if2_pc) 158// val if2_predHist = RegEnable(if1_gh.predHist, enable=if1_fire) 159// if2_ready := if3_ready && icache.io.tlb.resp.valid || !if2_valid 160// when (if1_fire) { if2_valid := true.B } 161// .elsewhen (if2_flush) { if2_valid := false.B } 162// .elsewhen (if2_fire) { if2_valid := false.B } 163 164// val npcGen = new PriorityMuxGenerator[UInt] 165// npcGen.register(true.B, RegNext(if1_npc), Some("stallPC")) 166// val if2_bp = bpu.io.out(0) 167 168// // if taken, bp_redirect should be true 169// // when taken on half RVI, we suppress this redirect signal 170 171// npcGen.register(if2_valid, Mux(if2_bp.taken, if2_bp.target, if2_snpc), Some("if2_target")) 172 173// if2_predicted_gh := if2_gh.update(if2_bp.hasNotTakenBrs, if2_bp.takenOnBr) 174 175// //********************** IF3 ****************************// 176// // if3 should wait for instructions resp to arrive 177// val if3_valid = RegInit(init = false.B) 178// val if4_ready = WireInit(false.B) 179// val if3_allValid = if3_valid && icache.io.resp.valid 180// val if3_fire = if3_allValid && if4_ready 181// val if3_pc = RegEnable(if2_pc, if2_fire) 182// val if3_snpc = RegEnable(if2_snpc, if2_fire) 183// val if3_predHist = RegEnable(if2_predHist, enable=if2_fire) 184// if3_ready := if4_ready && icache.io.resp.valid || !if3_valid 185// when (if3_flush) { 186// if3_valid := false.B 187// }.elsewhen (if2_fire && !if2_flush) { 188// if3_valid := true.B 189// }.elsewhen (if3_fire) { 190// if3_valid := false.B 191// } 192 193// val if3_bp = bpu.io.out(1) 194// if3_predicted_gh := if3_gh.update(if3_bp.hasNotTakenBrs, if3_bp.takenOnBr) 195 196 197// val prevHalfInstrReq = WireInit(0.U.asTypeOf(ValidUndirectioned(new PrevHalfInstr))) 198// // only valid when if4_fire 199// val hasPrevHalfInstrReq = prevHalfInstrReq.valid && HasCExtension.B 200 201// val if3_prevHalfInstr = RegInit(0.U.asTypeOf(ValidUndirectioned(new PrevHalfInstr))) 202 203// // 32-bit instr crosses 2 pages, and the higher 16-bit triggers page fault 204// val crossPageIPF = WireInit(false.B) 205 206// val if3_pendingPrevHalfInstr = if3_prevHalfInstr.valid && HasCExtension.B 207 208// // the previous half of RVI instruction waits until it meets its last half 209// val if3_prevHalfInstrMet = if3_pendingPrevHalfInstr && if3_prevHalfInstr.bits.npc === if3_pc && if3_valid 210// // set to invalid once consumed or redirect from backend 211// val if3_prevHalfConsumed = if3_prevHalfInstrMet && if3_fire 212// val if3_prevHalfFlush = if4_flush 213// when (if3_prevHalfFlush) { 214// if3_prevHalfInstr.valid := false.B 215// }.elsewhen (hasPrevHalfInstrReq) { 216// if3_prevHalfInstr.valid := true.B 217// }.elsewhen (if3_prevHalfConsumed) { 218// if3_prevHalfInstr.valid := false.B 219// } 220// when (hasPrevHalfInstrReq) { 221// if3_prevHalfInstr.bits := prevHalfInstrReq.bits 222// } 223// // when bp signal a redirect, we distinguish between taken and not taken 224// // if taken and saveHalfRVI is true, we do not redirect to the target 225 226// class IF3_PC_COMP extends XSModule { 227// val io = IO(new Bundle { 228// val if2_pc = Input(UInt(VAddrBits.W)) 229// val pc = Input(UInt(VAddrBits.W)) 230// val if2_valid = Input(Bool()) 231// val res = Output(Bool()) 232// }) 233// io.res := !io.if2_valid || io.if2_valid && io.if2_pc =/= io.pc 234// } 235// def if3_nextValidPCNotEquals(pc: UInt) = { 236// val comp = Module(new IF3_PC_COMP) 237// comp.io.if2_pc := if2_pc 238// comp.io.pc := pc 239// comp.io.if2_valid := if2_valid 240// comp.io.res 241// } 242 243// val if3_prevHalfNotMetRedirect = if3_pendingPrevHalfInstr && !if3_prevHalfInstrMet && if3_nextValidPCNotEquals(if3_prevHalfInstr.bits.npc) 244// val if3_predTakenRedirect = !if3_pendingPrevHalfInstr && if3_bp.taken && if3_nextValidPCNotEquals(if3_bp.target) 245// val if3_predNotTakenRedirect = !if3_pendingPrevHalfInstr && !if3_bp.taken && if3_nextValidPCNotEquals(if3_snpc) 246// // when pendingPrevHalfInstr, if3_GHInfo is set to the info of last prev half instr 247// // val if3_ghInfoNotIdenticalRedirect = !if3_pendingPrevHalfInstr && if3_GHInfo =/= if3_lastGHInfo && enableGhistRepair.B 248 249// if3_redirect := if3_valid && ( 250// // prevHalf does not match if3_pc and the next fetch packet is not snpc 251// if3_prevHalfNotMetRedirect && HasCExtension.B || 252// // pred taken and next fetch packet is not the predicted target 253// if3_predTakenRedirect || 254// // pred not taken and next fetch packet is not snpc 255// if3_predNotTakenRedirect 256// // GHInfo from last pred does not corresponds with this packet 257// // if3_ghInfoNotIdenticalRedirect 258// ) 259 260// val if3_target = WireInit(if3_snpc) 261 262// if3_target := Mux1H(Seq((if3_prevHalfNotMetRedirect -> if3_prevHalfInstr.bits.npc), 263// (if3_predTakenRedirect -> if3_bp.target), 264// (if3_predNotTakenRedirect -> if3_snpc))) 265 266// npcGen.register(if3_redirect, if3_target, Some("if3_target")) 267 268 269// //********************** IF4 ****************************// 270// val ftqEnqBuf_ready = Wire(Bool()) 271// val if4_ftqEnqPtr = Wire(new FtqPtr) 272// val if4_pd = RegEnable(icache.io.pd_out, if3_fire) 273// val if4_ipf = RegEnable(icacheResp.ipf || if3_prevHalfInstrMet && if3_prevHalfInstr.bits.ipf, if3_fire) 274// val if4_acf = RegEnable(icacheResp.acf, if3_fire) 275// val if4_crossPageIPF = RegEnable(crossPageIPF, if3_fire) 276// val if4_valid = RegInit(false.B) 277// val if4_fire = if4_valid && io.fetchPacket.ready && ftqEnqBuf_ready 278// val if4_pc = RegEnable(if3_pc, if3_fire) 279// val if4_snpc = RegEnable(if3_snpc, if3_fire) 280// // This is the real mask given from icache 281// val if4_mask = RegEnable(icacheResp.mask, if3_fire) 282 283 284// val if4_predHist = RegEnable(if3_predHist, enable=if3_fire) 285// // wait until prevHalfInstr written into reg 286// if4_ready := (io.fetchPacket.ready && !hasPrevHalfInstrReq && ftqEnqBuf_ready || !if4_valid) && GTimer() > 500.U 287// when (if4_flush) { 288// if4_valid := false.B 289// }.elsewhen (if3_fire && !if3_flush) { 290// if4_valid := Mux(if3_pendingPrevHalfInstr, if3_prevHalfInstrMet, true.B) 291// }.elsewhen (if4_fire) { 292// if4_valid := false.B 293// } 294 295// val if4_bp = Wire(new BranchPrediction) 296// if4_bp := bpu.io.out(2) 297 298// if4_predicted_gh := if4_gh.update(if4_bp.hasNotTakenBrs, if4_bp.takenOnBr) 299 300// def jal_offset(inst: UInt, rvc: Bool): SInt = { 301// Mux(rvc, 302// Cat(inst(12), inst(8), inst(10, 9), inst(6), inst(7), inst(2), inst(11), inst(5, 3), 0.U(1.W)).asSInt(), 303// Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)).asSInt() 304// ) 305// } 306// def br_offset(inst: UInt, rvc: Bool): SInt = { 307// Mux(rvc, 308// Cat(inst(12), inst(6, 5), inst(2), inst(11, 10), inst(4, 3), 0.U(1.W)).asSInt, 309// Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)).asSInt() 310// ) 311// } 312// val if4_instrs = if4_pd.instrs 313// val if4_jals = if4_bp.jalMask 314// val if4_jal_tgts = VecInit((0 until PredictWidth).map(i => (if4_pd.pc(i).asSInt + jal_offset(if4_instrs(i), if4_pd.pd(i).isRVC)).asUInt)) 315// val if4_brs = if4_bp.brMask 316// val if4_br_tgts = VecInit((0 until PredictWidth).map(i => (if4_pd.pc(i).asSInt + br_offset(if4_instrs(i), if4_pd.pd(i).isRVC)).asUInt)) 317// (0 until PredictWidth).foreach {i => 318// when (if4_jals(i)) { 319// if4_bp.targets(i) := if4_jal_tgts(i) 320// }.elsewhen (if4_brs(i)) { 321// if4_bp.targets(i) := if4_br_tgts(i) 322// } 323// } 324 325// // we need this to tell BPU the prediction of prev half 326// // because the prediction is with the start of each inst 327// val if4_prevHalfInstr = RegInit(0.U.asTypeOf(ValidUndirectioned(new PrevHalfInstr))) 328// val if4_pendingPrevHalfInstr = if4_prevHalfInstr.valid && HasCExtension.B 329// val if4_prevHalfInstrMet = if4_pendingPrevHalfInstr && if4_valid 330// val if4_prevHalfConsumed = if4_prevHalfInstrMet && if4_fire 331// val if4_prevHalfFlush = if4_flush 332 333// when (if4_prevHalfFlush) { 334// if4_prevHalfInstr.valid := false.B 335// }.elsewhen (if3_prevHalfConsumed) { 336// if4_prevHalfInstr.valid := if3_prevHalfInstr.valid 337// }.elsewhen (if4_prevHalfConsumed) { 338// if4_prevHalfInstr.valid := false.B 339// } 340 341// when (if3_prevHalfConsumed) { 342// if4_prevHalfInstr.bits := if3_prevHalfInstr.bits 343// } 344 345// prevHalfInstrReq.valid := if4_fire && if4_bp.saveHalfRVI && HasCExtension.B 346 347// // // this is result of the last half RVI 348// prevHalfInstrReq.bits.pc := if4_pd.pc(PredictWidth-1) 349// prevHalfInstrReq.bits.npc := snpc(if4_pc) 350// prevHalfInstrReq.bits.instr := if4_pd.instrs(PredictWidth-1)(15, 0) 351// prevHalfInstrReq.bits.ipf := if4_ipf 352 353// class IF4_PC_COMP extends XSModule { 354// val io = IO(new Bundle { 355// val if2_pc = Input(UInt(VAddrBits.W)) 356// val if3_pc = Input(UInt(VAddrBits.W)) 357// val pc = Input(UInt(VAddrBits.W)) 358// val if2_valid = Input(Bool()) 359// val if3_valid = Input(Bool()) 360// val res = Output(Bool()) 361// }) 362// io.res := io.if3_valid && io.if3_pc =/= io.pc || 363// !io.if3_valid && (io.if2_valid && io.if2_pc =/= io.pc) || 364// !io.if3_valid && !io.if2_valid 365// } 366// def if4_nextValidPCNotEquals(pc: UInt) = { 367// val comp = Module(new IF4_PC_COMP) 368// comp.io.if2_pc := if2_pc 369// comp.io.if3_pc := if3_pc 370// comp.io.pc := pc 371// comp.io.if2_valid := if2_valid 372// comp.io.if3_valid := if3_valid 373// comp.io.res 374// } 375 376// val if4_prevHalfNextNotMet = hasPrevHalfInstrReq && if4_nextValidPCNotEquals(prevHalfInstrReq.bits.pc+2.U) 377// val if4_predTakenRedirect = if4_bp.taken && if4_nextValidPCNotEquals(if4_bp.target) 378// val if4_predNotTakenRedirect = !if4_bp.taken && if4_nextValidPCNotEquals(if4_snpc) 379// // val if4_ghInfoNotIdenticalRedirect = if4_GHInfo =/= if4_lastGHInfo && enableGhistRepair.B 380 381// if4_redirect := if4_valid && ( 382// // when if4 has a lastHalfRVI, but the next fetch packet is not snpc 383// // if4_prevHalfNextNotMet || 384// // when if4 preds taken, but the pc of next fetch packet is not the target 385// if4_predTakenRedirect || 386// // when if4 preds not taken, but the pc of next fetch packet is not snpc 387// if4_predNotTakenRedirect 388// // GHInfo from last pred does not corresponds with this packet 389// // if4_ghInfoNotIdenticalRedirect 390// ) 391 392// val if4_target = WireInit(if4_snpc) 393 394// if4_target := Mux(if4_bp.taken, if4_bp.target, if4_snpc) 395 396// npcGen.register(if4_redirect, if4_target, Some("if4_target")) 397 398// when (if4_fire) { 399// final_gh := if4_predicted_gh 400// } 401// if4_gh := final_gh 402// if3_gh := Mux(if4_valid, if4_predicted_gh, if4_gh) 403// if2_gh := Mux(if3_valid && !if3_flush, if3_predicted_gh, if3_gh) 404// if1_gh := Mux(if2_valid && !if2_flush, if2_predicted_gh, if2_gh) 405 406// // ***************** Ftq enq buffer ******************** 407// val toFtqBuf = Wire(new FtqEntry) 408// val ftqEnqBuf = RegEnable(toFtqBuf, enable=if4_fire) 409// val ftqEnqBuf_valid = RegInit(false.B) 410// val ftqLeftOne = WireInit(false.B) // TODO: to be replaced 411// ftqEnqBuf_ready := io.toFtq.ready && !(io.ftqLeftOne && ftqEnqBuf_valid) 412// if4_ftqEnqPtr := Mux(ftqEnqBuf_valid, io.ftqEnqPtr+1.U, io.ftqEnqPtr) 413// when (io.redirect.valid) { ftqEnqBuf_valid := false.B } 414// .elsewhen (if4_fire) { ftqEnqBuf_valid := true.B } 415// .elsewhen (io.toFtq.fire) { ftqEnqBuf_valid := false.B } 416 417// io.toFtq.valid := ftqEnqBuf_valid 418// io.toFtq.bits := ftqEnqBuf 419 420// toFtqBuf := DontCare 421// toFtqBuf.ftqPC := if4_pc 422// toFtqBuf.lastPacketPC.valid := if4_pendingPrevHalfInstr 423// toFtqBuf.lastPacketPC.bits := if4_prevHalfInstr.bits.pc 424 425// toFtqBuf.hist := final_gh 426// toFtqBuf.predHist := if4_predHist.asTypeOf(new GlobalHistory) 427// toFtqBuf.rasSp := bpu.io.brInfo.rasSp 428// toFtqBuf.rasTop := bpu.io.brInfo.rasTop 429// toFtqBuf.specCnt := bpu.io.brInfo.specCnt 430// toFtqBuf.metas := bpu.io.brInfo.metas 431 432// // For perf counters 433// toFtqBuf.pd := if4_pd.pd 434 435 436// val if4_jmpIdx = WireInit(if4_bp.jmpIdx) 437// val if4_taken = WireInit(if4_bp.taken) 438// val if4_real_valids = if4_pd.mask & 439// (Fill(PredictWidth, !if4_taken) | 440// (Fill(PredictWidth, 1.U(1.W)) >> (~if4_jmpIdx))) 441 442// val cfiIsCall = if4_pd.pd(if4_jmpIdx).isCall 443// val cfiIsRet = if4_pd.pd(if4_jmpIdx).isRet 444// val cfiIsRVC = if4_pd.pd(if4_jmpIdx).isRVC 445// val cfiIsJalr = if4_pd.pd(if4_jmpIdx).isJalr 446// toFtqBuf.cfiIsCall := cfiIsCall 447// toFtqBuf.cfiIsRet := cfiIsRet 448// toFtqBuf.cfiIsJalr := cfiIsJalr 449// toFtqBuf.cfiIsRVC := cfiIsRVC 450// toFtqBuf.cfiIndex.valid := if4_taken 451// toFtqBuf.cfiIndex.bits := if4_jmpIdx 452 453// toFtqBuf.br_mask := if4_bp.brMask.asTypeOf(Vec(PredictWidth, Bool())) 454// toFtqBuf.rvc_mask := VecInit(if4_pd.pd.map(_.isRVC)) 455// toFtqBuf.valids := if4_real_valids.asTypeOf(Vec(PredictWidth, Bool())) 456// toFtqBuf.target := Mux(if4_taken, if4_target, if4_snpc) 457 458 459 460// val r = io.redirect 461// val cfiUpdate = io.redirect.bits.cfiUpdate 462// when (r.valid) { 463// val isMisPred = r.bits.level === 0.U 464// val b = cfiUpdate 465// val oldGh = b.hist 466// val sawNTBr = b.sawNotTakenBranch 467// val isBr = b.pd.isBr 468// val taken = Mux(isMisPred, b.taken, b.predTaken) 469// val updatedGh = oldGh.update(sawNTBr || isBr, isBr && taken) 470// final_gh := updatedGh 471// if1_gh := updatedGh 472// } 473 474// npcGen.register(io.redirect.valid, io.redirect.bits.cfiUpdate.target, Some("backend_redirect")) 475// npcGen.register(RegNext(reset.asBool) && !reset.asBool, resetVector.U(VAddrBits.W), Some("reset_vector")) 476 477// if1_npc := npcGen() 478 479 480// icache.io.req.valid := if1_fire 481// icache.io.resp.ready := if4_ready 482// icache.io.req.bits.addr := if1_npc 483// icache.io.req.bits.mask := mask(if1_npc) 484// icache.io.flush := Cat(if3_flush, if2_flush) 485// icache.io.mem_grant <> io.icacheMemGrant 486// icache.io.fencei := io.fencei 487// icache.io.prev.valid := if3_prevHalfInstrMet 488// icache.io.prev.bits := if3_prevHalfInstr.bits.instr 489// icache.io.prev_ipf := if3_prevHalfInstr.bits.ipf 490// icache.io.prev_pc := if3_prevHalfInstr.bits.pc 491// icache.io.mmio_acquire <> io.mmio_acquire 492// icache.io.mmio_grant <> io.mmio_grant 493// icache.io.mmio_flush <> io.mmio_flush 494// io.icacheMemAcq <> icache.io.mem_acquire 495// io.l1plusFlush := icache.io.l1plusflush 496// io.prefetchTrainReq := icache.io.prefetchTrainReq 497// io.error <> icache.io.error 498 499// bpu.io.ctrl := RegNext(io.bp_ctrl) 500// bpu.io.commit <> io.commitUpdate 501// bpu.io.redirect <> io.redirect 502 503// bpu.io.inFire(0) := if1_fire 504// bpu.io.inFire(1) := if2_fire 505// bpu.io.inFire(2) := if3_fire 506// bpu.io.inFire(3) := if4_fire 507// bpu.io.in.pc := if1_npc 508// bpu.io.in.hist := if1_gh.asUInt 509// bpu.io.in.inMask := mask(if1_npc) 510// bpu.io.predecode.mask := if4_pd.mask 511// bpu.io.predecode.lastHalf := if4_pd.lastHalf 512// bpu.io.predecode.pd := if4_pd.pd 513// bpu.io.predecode.hasLastHalfRVI := if4_prevHalfInstrMet 514 515 516// when (if3_prevHalfInstrMet && icacheResp.ipf && !if3_prevHalfInstr.bits.ipf) { 517// crossPageIPF := true.B // higher 16 bits page fault 518// } 519 520// val fetchPacketValid = if4_valid && !io.redirect.valid && ftqEnqBuf_ready 521// val fetchPacketWire = Wire(new FetchPacket) 522 523// fetchPacketWire.mask := if4_real_valids 524// //RVC expand 525// val expandedInstrs = Wire(Vec(PredictWidth, UInt(32.W))) 526// for(i <- 0 until PredictWidth){ 527// val expander = Module(new RVCExpander) 528// expander.io.in := if4_pd.instrs(i) 529// expandedInstrs(i) := expander.io.out.bits 530// } 531// fetchPacketWire.instrs := expandedInstrs 532 533// fetchPacketWire.pc := if4_pd.pc 534// fetchPacketWire.foldpc := if4_pd.pc.map(i => XORFold(i(VAddrBits-1,1), MemPredPCWidth)) 535 536// fetchPacketWire.pdmask := if4_pd.mask 537// fetchPacketWire.pd := if4_pd.pd 538// fetchPacketWire.ipf := if4_ipf 539// fetchPacketWire.acf := if4_acf 540// fetchPacketWire.crossPageIPFFix := if4_crossPageIPF 541// fetchPacketWire.ftqPtr := if4_ftqEnqPtr 542 543// // predTaken Vec 544// fetchPacketWire.pred_taken := if4_bp.takens 545 546// io.fetchPacket.bits := fetchPacketWire 547// io.fetchPacket.valid := fetchPacketValid 548 549// if (!env.FPGAPlatform && env.EnablePerfDebug) { 550// val predictor_s3 = RegEnable(Mux(if3_redirect, 1.U(log2Up(4).W), 0.U(log2Up(4).W)), if3_fire) 551// val predictor_s4 = Mux(if4_redirect, 2.U, predictor_s3) 552// val predictor = predictor_s4 553// toFtqBuf.metas.map(_.predictor := predictor) 554 555// toFtqBuf.metas.zipWithIndex.foreach{ case(x,i) => 556// x.predictor := predictor 557 558// x.ubtbAns := bpu.io.brInfo.metas(i).ubtbAns 559// x.btbAns := bpu.io.brInfo.metas(i).btbAns 560// x.tageAns := bpu.io.brInfo.metas(i).tageAns 561// x.rasAns := bpu.io.brInfo.metas(i).rasAns // Is this right? 562// x.loopAns := bpu.io.brInfo.metas(i).loopAns 563// } 564// } 565 566// // TODO: perfs 567// // frontend redirect from each stage 568// XSPerfAccumulate("if2_redirect", if2_valid && if2_bp.taken && !if2_flush) 569// XSPerfAccumulate("if2_redirect_fired", if2_fire && if2_bp.taken && !if2_flush) 570// XSPerfAccumulate("if3_redirect", if3_valid && if3_redirect && !if3_flush) 571// XSPerfAccumulate("if3_redirect_fired", if3_fire && if3_redirect && !if3_flush) 572// XSPerfAccumulate("if4_redirect", if4_valid && if4_redirect && !if4_flush) 573// XSPerfAccumulate("if4_redirect_fired", if4_fire && if4_redirect && !if4_flush) 574 575// XSPerfAccumulate("if1_total_stall", !if2_allReady && if1_valid) 576// XSPerfAccumulate("if1_stall_from_icache_req", !icache.io.req.ready && if1_valid) 577// XSPerfAccumulate("if1_stall_from_if2", !if2_ready && if1_valid) 578// XSPerfAccumulate("if1_stall_from_bpu", !bpu.io.in_ready && if1_valid) 579// XSPerfAccumulate("itlb_stall", if2_valid && if3_ready && !icache.io.tlb.resp.valid) 580// XSPerfAccumulate("icache_resp_stall", if3_valid && if4_ready && !icache.io.resp.valid) 581// XSPerfAccumulate("if4_stall", if4_valid && !if4_fire) 582// XSPerfAccumulate("if4_stall_ibuffer", if4_valid && !io.fetchPacket.ready && ftqEnqBuf_ready) 583// XSPerfAccumulate("if4_stall_ftq", if4_valid && io.fetchPacket.ready && !ftqEnqBuf_ready) 584 585// XSPerfAccumulate("if3_prevHalfConsumed", if3_prevHalfConsumed) 586// XSPerfAccumulate("if4_prevHalfConsumed", if4_prevHalfConsumed) 587 588 589// // debug info 590// if (IFUDebug) { 591// XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n") 592// XSDebug(icache.io.flush(0).asBool, "Flush icache stage2...\n") 593// XSDebug(icache.io.flush(1).asBool, "Flush icache stage3...\n") 594// XSDebug(io.redirect.valid, p"Redirect from backend! target=${Hexadecimal(io.redirect.bits.cfiUpdate.target)}\n") 595 596// XSDebug("[IF1] v=%d fire=%d flush=%d pc=%x mask=%b\n", if1_valid, if1_fire, if1_flush, if1_npc, mask(if1_npc)) 597// XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_snpc) 598// XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x crossPageIPF=%d sawNTBrs=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, crossPageIPF, if3_bp.hasNotTakenBrs) 599// XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x crossPageIPF=%d sawNTBrs=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_crossPageIPF, if4_bp.hasNotTakenBrs) 600// XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", icache.io.req.valid, icache.io.req.ready, icache.io.req.bits.addr) 601// XSDebug("[IF1][ghr] hist=%b\n", if1_gh.asUInt) 602 603// XSDebug("[IF2][bp] taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n\n", if2_bp.taken, if2_bp.jmpIdx, if2_bp.hasNotTakenBrs, if2_bp.target, if2_bp.saveHalfRVI) 604// if2_gh.debug("if2") 605 606// XSDebug("[IF3][icacheResp] v=%d r=%d pc=%x mask=%b\n", icache.io.resp.valid, icache.io.resp.ready, icache.io.resp.bits.pc, icache.io.resp.bits.mask) 607// XSDebug("[IF3][bp] taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if3_bp.taken, if3_bp.jmpIdx, if3_bp.hasNotTakenBrs, if3_bp.target, if3_bp.saveHalfRVI) 608// XSDebug("[IF3][redirect]: v=%d, prevNMet=%d, predT=%d, predNT=%d\n", if3_redirect, if3_prevHalfNotMetRedirect, if3_predTakenRedirect, if3_predNotTakenRedirect) 609// // XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n", 610// // prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr) 611// XSDebug("[IF3][if3_prevHalfInstr] v=%d pc=%x npc=%x instr=%x ipf=%d\n\n", 612// if3_prevHalfInstr.valid, if3_prevHalfInstr.bits.pc, if3_prevHalfInstr.bits.npc, if3_prevHalfInstr.bits.instr, if3_prevHalfInstr.bits.ipf) 613// if3_gh.debug("if3") 614 615// XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) 616// XSDebug("[IF4][snpc]: %x, realMask=%b\n", if4_snpc, if4_mask) 617// XSDebug("[IF4][bp] taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) 618// XSDebug("[IF4][redirect]: v=%d, prevNotMet=%d, predT=%d, predNT=%d\n", if4_redirect, if4_prevHalfNextNotMet, if4_predTakenRedirect, if4_predNotTakenRedirect) 619// XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_instrs(if4_bp.jmpIdx), if4_jal_tgts(if4_bp.jmpIdx)) 620// XSDebug("[IF4][ prevHalfInstrReq] v=%d pc=%x npc=%x instr=%x ipf=%d\n", 621// prevHalfInstrReq.valid, prevHalfInstrReq.bits.pc, prevHalfInstrReq.bits.npc, prevHalfInstrReq.bits.instr, prevHalfInstrReq.bits.ipf) 622// XSDebug("[IF4][if4_prevHalfInstr] v=%d pc=%x npc=%x instr=%x ipf=%d\n", 623// if4_prevHalfInstr.valid, if4_prevHalfInstr.bits.pc, if4_prevHalfInstr.bits.npc, if4_prevHalfInstr.bits.instr, if4_prevHalfInstr.bits.ipf) 624// if4_gh.debug("if4") 625// XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d acf=%d crossPageIPF=%d\n", 626// io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask, io.fetchPacket.bits.ipf, io.fetchPacket.bits.acf, io.fetchPacket.bits.crossPageIPFFix) 627// for (i <- 0 until PredictWidth) { 628// XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", 629// io.fetchPacket.bits.mask(i), 630// io.fetchPacket.bits.instrs(i), 631// io.fetchPacket.bits.pc(i), 632// io.fetchPacket.bits.pd(i).isRVC, 633// io.fetchPacket.bits.pd(i).brType, 634// io.fetchPacket.bits.pd(i).isCall, 635// io.fetchPacket.bits.pd(i).isRet 636// ) 637// } 638// val b = ftqEnqBuf 639// XSDebug("[FtqEnqBuf] v=%d r=%d pc=%x cfiIndex(%d)=%d cfiIsCall=%d cfiIsRet=%d cfiIsJalr=%d cfiIsRVC=%d\n", 640// ftqEnqBuf_valid, ftqEnqBuf_ready, b.ftqPC, b.cfiIndex.valid, b.cfiIndex.bits, b.cfiIsCall, b.cfiIsRet, b.cfiIsJalr, b.cfiIsRVC) 641// XSDebug("[FtqEnqBuf] valids=%b br_mask=%b rvc_mask=%b hist=%x predHist=%x rasSp=%d rasTopAddr=%x rasTopCtr=%d\n", 642// b.valids.asUInt, b.br_mask.asUInt, b.rvc_mask.asUInt, b.hist.asUInt, b.predHist.asUInt, b.rasSp, b.rasTop.retAddr, b.rasTop.ctr) 643// XSDebug("[ToFTQ] v=%d r=%d leftOne=%d ptr=%d\n", io.toFtq.valid, io.toFtq.ready, io.ftqLeftOne, io.ftqEnqPtr.value) 644// } 645 646// } 647