xref: /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala (revision 98cfe81bc227fcb004cb17eeba2f56f63cf1dde9) 
1package xiangshan.backend.exu
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import xiangshan.backend.Bundles.{ExuInput, ExuOutput}
7import xiangshan.backend.datapath.DataConfig.DataConfig
8import xiangshan.backend.datapath.RdConfig._
9import xiangshan.backend.datapath.WbConfig.{FpWB, IntWB, WbConfig}
10import xiangshan.backend.fu.{FuConfig, FuType}
11import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler}
12
13case class ExeUnitParams(
14  fuConfigs     : Seq[FuConfig],
15  wbPortConfigs : Seq[WbConfig],
16  rfrPortConfigs: Seq[Seq[RdConfig]],
17)(
18  implicit
19  val schdType: SchedulerType,
20) {
21  val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max
22  val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max
23  val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max
24  val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max
25  val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max
26  val numSrc: Int = fuConfigs.map(_.numSrc).max
27  val dataBitsMax: Int = fuConfigs.map(_.dataBits).max
28  val readIntRf: Boolean = numIntSrc > 0
29  val readFpRf: Boolean = numFpSrc > 0
30  val readVecRf: Boolean = numVecSrc > 0
31  val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _)
32  val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _)
33  val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _)
34  val writeVfRf: Boolean = writeFpRf || writeVecRf
35  val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _)
36  val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _)
37  val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _)
38  val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _)
39  val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _)
40  val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted
41  val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _)
42  val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _)
43  val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _)
44  val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _)
45  val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger
46  val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _)
47  val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _)
48  val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _)
49  val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _)
50  val wbPregIdxWidth = if (wbPortConfigs.nonEmpty) wbPortConfigs.map(_.pregIdxWidth).max else 0
51
52  protected val latencyCertain = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_&&_)
53  val fuLatencyMap = if (latencyCertain) Some(fuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None
54  val latencyValMax = fuLatencyMap.map(x => x.map(_._2).max)
55
56  def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _)
57
58  def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _)
59
60  def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _)
61
62  def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _)
63
64  def hasLoadFu = fuConfigs.map(_.fuType == FuType.ldu).reduce(_ || _)
65
66  def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _)
67
68  def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _)
69
70  def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _)
71
72  def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu
73
74  def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _)
75
76  def getSrcDataType(srcIdx: Int): Set[DataConfig] = {
77    fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _)
78  }
79
80  def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _)
81
82  def getWBSource: SchedulerType = {
83    schdType
84  }
85
86  def hasCrossWb: Boolean = {
87    schdType match {
88      case IntScheduler() => writeFpRf || writeVecRf
89      case VfScheduler() => writeIntRf
90      case _ => false
91    }
92  }
93
94  def canAccept(fuType: UInt): Bool = {
95    Cat(fuConfigs.map(_.fuType.U === fuType)).orR
96  }
97
98  def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _)
99
100  def getIntWBPort = {
101    wbPortConfigs.collectFirst {
102      case x: IntWB => x
103    }
104  }
105
106  def getFpWBPort = {
107    wbPortConfigs.collectFirst {
108      case x: FpWB => x
109    }
110  }
111
112  def getRfReadDataCfgSet: Seq[Set[DataConfig]] = {
113    val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet)
114    val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]()))
115
116    val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 })
117
118    exuSrcsCfgSet
119  }
120
121  def genExuModule(implicit p: Parameters): ExeUnit = {
122    new ExeUnit(this)
123  }
124
125  def genExuInputBundle(implicit p: Parameters): ExuInput = {
126    new ExuInput(this)
127  }
128
129  def genExuOutputBundle(implicit p: Parameters): ExuOutput = {
130    new ExuOutput(this)
131  }
132}
133