1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import utils.XSDebug 23import xiangshan._ 24import xiangshan.backend.fu.fpu.IntToFP 25import xiangshan.backend.fu.{CSR, FUWithRedirect, Fence, FenceToSbuffer} 26 27class FenceIO(implicit p: Parameters) extends XSBundle { 28 val sfence = Output(new SfenceBundle) 29 val fencei = Output(Bool()) 30 val sbuffer = new FenceToSbuffer 31} 32 33class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config: ExuConfig) { 34 val disableSfence = WireInit(false.B) 35 val csr_frm = WireInit(0.U(3.W)) 36 37 val hasRedirect = config.fuConfigs.zip(supportedFunctionUnits).filter(_._1.hasRedirect).map(_._2) 38 println(s"${supportedFunctionUnits} ${hasRedirect} hasRedirect: ${hasRedirect.length}") 39 if (hasRedirect.nonEmpty) { 40 require(hasRedirect.length <= 1) 41 io.out.bits.redirectValid := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOutValid 42 io.out.bits.redirect := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOut 43 } 44 45 if (config.fuConfigs.contains(csrCfg)) { 46 val csr = supportedFunctionUnits.collectFirst{ 47 case c: CSR => c 48 }.get 49 csr.csrio <> csrio.get 50 disableSfence := csr.csrio.disableSfence 51 csr_frm := csr.csrio.fpu.frm 52 } 53 54 if (config.fuConfigs.contains(fenceCfg)) { 55 val fence = supportedFunctionUnits.collectFirst{ 56 case f: Fence => f 57 }.get 58 fenceio.get.sfence <> fence.sfence 59 fenceio.get.fencei <> fence.fencei 60 fenceio.get.sbuffer <> fence.toSbuffer 61 fence.io.out.ready := true.B 62 fence.disableSfence := disableSfence 63 } 64 65 if (config.fuConfigs.contains(i2fCfg)) { 66 val i2f = supportedFunctionUnits.collectFirst { 67 case i: IntToFP => i 68 }.get 69 val instr_rm = io.fromInt.bits.uop.ctrl.fpu.rm 70 i2f.rm := Mux(instr_rm =/= 7.U, instr_rm, csr_frm) 71 } 72 73 if (config.readIntRf) { 74 val in = io.fromInt 75 val out = io.out 76 XSDebug(in.valid, p"fromInt(${in.valid} ${in.ready}) toInt(${out.valid} ${out.ready})\n") 77 XSDebug(io.redirect.valid, p"Redirect:(${io.redirect.valid}) roqIdx:${io.redirect.bits.roqIdx}\n") 78 XSDebug(in.valid, p"src1:${Hexadecimal(in.bits.src(0))} src2:${Hexadecimal(in.bits.src(1))} " + 79 p"func:${Binary(in.bits.uop.ctrl.fuOpType)} pc:${Hexadecimal(in.bits.uop.cf.pc)} roqIdx:${in.bits.uop.roqIdx}\n") 80 XSDebug(out.valid, p"out res:${Hexadecimal(out.bits.data)} roqIdx:${out.bits.uop.roqIdx}\n") 81 } 82 83} 84 85class AluExeUnit(implicit p: Parameters) extends ExeUnit(AluExeUnitCfg) 86class JumpCSRExeUnit(implicit p: Parameters) extends ExeUnit(JumpCSRExeUnitCfg) 87class JumpExeUnit(implicit p: Parameters) extends ExeUnit(JumpExeUnitCfg) 88 89object ExeUnit { 90 def apply(cfg: ExuConfig)(implicit p: Parameters): ExeUnit = { 91 cfg match { 92 case JumpExeUnitCfg => Module(new JumpExeUnit) 93 case AluExeUnitCfg => Module(new AluExeUnit) 94 case MulDivExeUnitCfg => Module(new MulDivExeUnit) 95 case JumpCSRExeUnitCfg => Module(new JumpCSRExeUnit) 96 case FmacExeUnitCfg => Module(new FmacExeUnit) 97 case FmiscExeUnitCfg => Module(new FmiscExeUnit) 98 case _ => null 99 } 100 } 101}