feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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feat(dfx): integerate dfx components (#4312)

area(EXU): add parameter `needCopySrc` in FuConfig (#4063)

area(exu): data signals only pipe once in exu

area(exu): ctrl signals only pipe once in exu

area(backend): only use startAddr in pcMem

feat(dbltrp) : add support for critical error (#3793)

fix(FuUnit, clkgate): use fu.io.in/out.fire to control its clkgate enable signal (#3751)

power(backend): add clock gate for Rob and IssueQueue (#3602)

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inva

NewCSR: add full illegal check to `sfence` and the insts in `Svinval` extension

* Move the permission check for some insts to DecodeUnit.
* These insts are `sfence.vma`, `sinval.vma`, `sfence.w.inval`, `sfence.inval.ir`, `hfence.gvma`, `hinval.gvma`, `hfence.vvma` and `hinval.vvma`.

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NewCSR: make XRET use redirect bundle to pass target instead of csr-rob direct connection

* TODO: remove isXRet signal from RobCSRIO.
* Add ftqIdx,ftqOffset in CSR Fu.
* XRet need not flushPipe

NewCSR: add IMSIC

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

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Backend: fix Uncertain Layency Fu's clock gate (#3085)

VPU: fix vfreduction bug; remove redundant logic for scalar compute (#3065)

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbite

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbiter
wbtorob:
fix writebacknum count: delete extra count for exu which cannot be compressed

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ExeUnit: in1toN in.ready not dependent on acceptVec

Exu: connect V0Wen VlWen

vtype: add valid signal for vsetvl instruction when calculate output

ExeUnit: add fpWbPort assert

Merge branch 'master' into vlsu-merge-master-0504

Utility: Fix wrong use case of XSError in XiangShan

Some XSError message uses `s` to format strings with some information
peeked from the circuit. It does not peek the correct information from RTL
a

Utility: Fix wrong use case of XSError in XiangShan

Some XSError message uses `s` to format strings with some information
peeked from the circuit. It does not peek the correct information from RTL
and makes the module itself fail to dedup. This commit fixes this by
replacing `s` with `p`.

Signed-off-by: Yangyu Chen <[email protected]>

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rv64v: fix the logic of writing vtype for vsetvl instruction

Merge branch 'master' into vlsu-tmp-master