1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility._ 25import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 26import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 27import xiangshan.{AddrTransType, FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 28import xiangshan.backend.datapath.WbConfig.{PregWB, _} 29import xiangshan.backend.fu.FuType 30import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm} 31import xiangshan.backend.fu.fpu.Bundles.Frm 32import xiangshan.backend.fu.wrapper.{CSRInput, CSRToDecode} 33 34class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 35 val flush = Flipped(ValidIO(new Redirect())) 36 val in = Flipped(DecoupledIO(new ExuInput(params))) 37 val out = DecoupledIO(new ExuOutput(params)) 38 val csrin = Option.when(params.hasCSR)(new CSRInput) 39 val csrio = Option.when(params.hasCSR)(new CSRFileIO) 40 val csrToDecode = Option.when(params.hasCSR)(Output(new CSRToDecode)) 41 val fenceio = Option.when(params.hasFence)(new FenceIO) 42 val frm = Option.when(params.needSrcFrm)(Input(Frm())) 43 val vxrm = Option.when(params.needSrcVxrm)(Input(Vxrm())) 44 val vtype = Option.when(params.writeVConfig)((Valid(new VType))) 45 val vlIsZero = Option.when(params.writeVConfig)(Output(Bool())) 46 val vlIsVlmax = Option.when(params.writeVConfig)(Output(Bool())) 47 val instrAddrTransType = Option.when(params.hasJmpFu || params.hasBrhFu)(Input(new AddrTransType)) 48} 49 50class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 51 override def shouldBeInlined: Boolean = false 52 53 lazy val module = new ExeUnitImp(this)(p, exuParams) 54} 55 56class ExeUnitImp( 57 override val wrapper: ExeUnit 58)(implicit 59 p: Parameters, exuParams: ExeUnitParams 60) extends LazyModuleImp(wrapper) with HasXSParameter{ 61 private val fuCfgs = exuParams.fuConfigs 62 63 val io = IO(new ExeUnitIO(exuParams)) 64 65 val funcUnits = fuCfgs.map(cfg => { 66 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 67 val module = cfg.fuGen(p, cfg) 68 module 69 }) 70 71 if (EnableClockGate) { 72 fuCfgs.zip(funcUnits).foreach { case (cfg, fu) => 73 val clk_en = WireInit(false.B) 74 val fuVld_en = WireInit(false.B) 75 val fuVld_en_reg = RegInit(false.B) 76 val uncer_en_reg = RegInit(false.B) 77 78 def latReal: Int = cfg.latency.latencyVal.getOrElse(0) 79 def extralat: Int = cfg.latency.extraLatencyVal.getOrElse(0) 80 81 val uncerLat = cfg.latency.uncertainEnable.nonEmpty 82 val lat0 = (latReal == 0 && !uncerLat).asBool 83 val latN = (latReal > 0 && !uncerLat).asBool 84 85 val fuVldVec = (io.in.valid && latN) +: Seq.fill(latReal)(RegInit(false.B)) 86 val fuRdyVec = Seq.fill(latReal)(Wire(Bool())) :+ io.out.ready 87 88 for (i <- 0 until latReal) { 89 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 90 } 91 92 for (i <- 1 to latReal) { 93 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 94 fuVldVec(i) := fuVldVec(i - 1) 95 }.elsewhen(fuRdyVec(i)) { 96 fuVldVec(i) := false.B 97 } 98 } 99 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 100 fuVld_en_reg := fuVld_en 101 102 when(uncerLat.asBool && io.in.fire) { 103 uncer_en_reg := true.B 104 }.elsewhen(uncerLat.asBool && io.out.fire) { 105 uncer_en_reg := false.B 106 } 107 108 when(lat0 && io.in.fire) { 109 clk_en := true.B 110 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 111 clk_en := true.B 112 }.elsewhen(uncerLat.asBool && io.in.fire || uncer_en_reg) { 113 clk_en := true.B 114 } 115 116 if (cfg.ckAlwaysEn) { 117 clk_en := true.B 118 } 119 120 fu.clock := ClockGate(false.B, clk_en, clock) 121 XSPerfAccumulate(s"clock_gate_en_${fu.cfg.name}", clk_en) 122 } 123 } 124 125 val busy = RegInit(false.B) 126 if (exuParams.latencyCertain){ 127 busy := false.B 128 } 129 else { 130 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 131 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 132 busy := false.B 133 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 134 busy := false.B 135 }.elsewhen(io.out.fire) { 136 busy := false.B 137 }.elsewhen(io.in.fire) { 138 busy := true.B 139 } 140 } 141 142 exuParams.wbPortConfigs.map{ 143 x => x match { 144 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 145 s"${exuParams.name}: WbPort must priority=0 or priority=1") 146 case FpWB(port, priority) => assert(priority >= 0 && priority <= 2, 147 s"${exuParams.name}: WbPort must priority=0 or priority=1") 148 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 149 s"${exuParams.name}: WbPort must priority=0 or priority=1") 150 case _ => 151 } 152 } 153 val intWbPort = exuParams.getIntWBPort 154 if (intWbPort.isDefined){ 155 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 156 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 157 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 158 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 159 samePort.wbPortConfigs.map( 160 x => x match { 161 case IntWB(port, priority) => { 162 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 163 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 164 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 165 } 166 case _ => 167 } 168 ) 169 ) 170 } 171 val fpWbPort = exuParams.getFpWBPort 172 if (fpWbPort.isDefined) { 173 val sameFpPortExuParam = backendParams.allExuParams.filter(_.getFpWBPort.isDefined) 174 .filter(_.getFpWBPort.get.port == fpWbPort.get.port) 175 val samePortOneCertainOneUncertain = sameFpPortExuParam.map(_.latencyCertain).contains(true) && sameFpPortExuParam.map(_.latencyCertain).contains(false) 176 if (samePortOneCertainOneUncertain) sameFpPortExuParam.map(samePort => 177 samePort.wbPortConfigs.map( 178 x => x match { 179 case FpWB(port, priority) => { 180 if (!samePort.latencyCertain) assert(priority == sameFpPortExuParam.size - 1, 181 s"${samePort.name}: FpWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameFpPortExuParam.size - 1})") 182 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 183 } 184 case _ => 185 } 186 ) 187 ) 188 } 189 val vfWbPort = exuParams.getVfWBPort 190 if (vfWbPort.isDefined) { 191 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 192 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 193 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 194 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 195 samePort.wbPortConfigs.map( 196 x => x match { 197 case VfWB(port, priority) => { 198 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 199 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 200 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 201 } 202 case _ => 203 } 204 ) 205 ) 206 } 207 if(backendParams.debugEn) { 208 dontTouch(io.out.ready) 209 } 210 // rob flush --> funcUnits 211 funcUnits.zipWithIndex.foreach { case (fu, i) => 212 fu.io.flush <> io.flush 213 } 214 215 def acceptCond(input: ExuInput): Seq[Bool] = { 216 input.params.fuConfigs.map(_.fuSel(input)) 217 } 218 219 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 220 221 // ExeUnit.in <---> Dispatcher.in 222 in1ToN.io.in.valid := io.in.valid && !busy 223 in1ToN.io.in.bits := io.in.bits 224 io.in.ready := !busy && in1ToN.io.in.ready 225 226 // Dispatcher.out <---> FunctionUnits 227 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 228 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 229 sink.valid := source.valid 230 source.ready := sink.ready 231 232 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 233 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 234 sink.bits.data.imm := source.bits.imm 235 sink.bits.ctrl.fuOpType := source.bits.fuOpType 236 sink.bits.ctrl.robIdx := source.bits.robIdx 237 sink.bits.ctrl.pdest := source.bits.pdest 238 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 239 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 240 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 241 sink.bits.ctrl.v0Wen .foreach(x => x := source.bits.v0Wen.get) 242 sink.bits.ctrl.vlWen .foreach(x => x := source.bits.vlWen.get) 243 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 244 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 245 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 246 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 247 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 248 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 249 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 250 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFpToVecInst := 0.U) 251 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP32Instr := 0.U) 252 sink.bits.ctrl.vpu .foreach(x => x.fpu.isFP64Instr := 0.U) 253 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 254 } 255 256 private val OutresVecs = funcUnits.map { fu => 257 def latDiff :Int = fu.cfg.latency.extraLatencyVal.getOrElse(0) 258 val OutresVec = fu.io.out.bits.res +: Seq.fill(latDiff)(Reg(chiselTypeOf(fu.io.out.bits.res))) 259 for (i <- 1 to latDiff) { 260 OutresVec(i) := OutresVec(i - 1) 261 } 262 OutresVec 263 } 264 OutresVecs.foreach(vec => vec.foreach(res =>dontTouch(res))) 265 266 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 267 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 268 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 269 private val fuOutresVec = OutresVecs.map(_.last) 270 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = fuOutresVec.map(_.redirect) 271 272 // Assume that one fu can only write int or fp or vec, 273 // otherwise, wenVec should be assigned to wen in fu. 274 private val fuIntWenVec = funcUnits.map(x => x.cfg.needIntWen.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 275 private val fuFpWenVec = funcUnits.map( x => x.cfg.needFpWen.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 276 private val fuVecWenVec = funcUnits.map(x => x.cfg.needVecWen.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 277 private val fuV0WenVec = funcUnits.map(x => x.cfg.needV0Wen.B && x.io.out.bits.ctrl.v0Wen.getOrElse(false.B)) 278 private val fuVlWenVec = funcUnits.map(x => x.cfg.needVlWen.B && x.io.out.bits.ctrl.vlWen.getOrElse(false.B)) 279 // FunctionUnits <---> ExeUnit.out 280 281 private val outDataVec = Seq( 282 Some(fuOutresVec.map(_.data)), 283 Option.when(funcUnits.exists(_.cfg.writeIntRf)) 284 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuout) => fuout.data}), 285 Option.when(funcUnits.exists(_.cfg.writeFpRf)) 286 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuout) => fuout.data}), 287 Option.when(funcUnits.exists(_.cfg.writeVecRf)) 288 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuout) => fuout.data}), 289 Option.when(funcUnits.exists(_.cfg.writeV0Rf)) 290 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuout) => fuout.data}), 291 Option.when(funcUnits.exists(_.cfg.writeVlRf)) 292 (funcUnits.zip(fuOutresVec).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuout) => fuout.data}), 293 ).flatten 294 private val outDataValidOH = Seq( 295 Some(fuOutValidOH), 296 Option.when(funcUnits.exists(_.cfg.writeIntRf)) 297 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeIntRf}.map{ case(_, fuoutOH) => fuoutOH}), 298 Option.when(funcUnits.exists(_.cfg.writeFpRf)) 299 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeFpRf}.map{ case(_, fuoutOH) => fuoutOH}), 300 Option.when(funcUnits.exists(_.cfg.writeVecRf)) 301 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVecRf}.map{ case(_, fuoutOH) => fuoutOH}), 302 Option.when(funcUnits.exists(_.cfg.writeV0Rf)) 303 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeV0Rf}.map{ case(_, fuoutOH) => fuoutOH}), 304 Option.when(funcUnits.exists(_.cfg.writeVlRf)) 305 (funcUnits.zip(fuOutValidOH).filter{ case (fu, _) => fu.cfg.writeVlRf}.map{ case(_, fuoutOH) => fuoutOH}), 306 ).flatten 307 308 io.out.valid := Cat(fuOutValidOH).orR 309 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 310 311 // select one fu's result 312 io.out.bits.data := VecInit(outDataVec.zip(outDataValidOH).map{ case(data, validOH) => Mux1H(validOH, data)}) 313 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 314 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 315 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 316 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 317 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 318 io.out.bits.v0Wen.foreach(x => x := Mux1H(fuOutValidOH, fuV0WenVec)) 319 io.out.bits.vlWen.foreach(x => x := Mux1H(fuOutValidOH, fuVlWenVec)) 320 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 321 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 322 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 323 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 324 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 325 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 326 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 327 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 328 329 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 330 fuio => 331 exuio <> fuio 332 fuio.exception := DelayN(exuio.exception, 2) 333 fuio.robDeqPtr := DelayN(exuio.robDeqPtr, 2) 334 })) 335 io.csrin.foreach(exuio => funcUnits.foreach(fu => fu.io.csrin.foreach{fuio => fuio := exuio})) 336 io.csrToDecode.foreach(toDecode => funcUnits.foreach(fu => fu.io.csrToDecode.foreach(fuOut => toDecode := fuOut))) 337 338 io.vtype.foreach(exuio => funcUnits.foreach(fu => fu.io.vtype.foreach(fuio => exuio := fuio))) 339 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 340 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 341 io.vxrm.foreach(exuio => funcUnits.foreach(fu => fu.io.vxrm.foreach(fuio => fuio <> exuio))) 342 io.vlIsZero.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsZero.foreach(fuio => exuio := fuio))) 343 io.vlIsVlmax.foreach(exuio => funcUnits.foreach(fu => fu.io.vlIsVlmax.foreach(fuio => exuio := fuio))) 344 io.instrAddrTransType.foreach(exuio => funcUnits.foreach(fu => fu.io.instrAddrTransType.foreach(fuio => fuio := exuio))) 345 346 // debug info 347 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 348 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 349 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 350} 351 352class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 353 val in = Flipped(DecoupledIO(gen)) 354 355 val out = Vec(n, DecoupledIO(gen)) 356} 357 358class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 359 (implicit p: Parameters) 360 extends Module { 361 362 val io = IO(new DispatcherIO(gen, n)) 363 364 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 365 366 XSError(io.in.valid && PopCount(acceptVec) > 1.U, p"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 367 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 368 369 io.out.zipWithIndex.foreach { case (out, i) => 370 out.valid := acceptVec(i) && io.in.valid 371 out.bits := io.in.bits 372 } 373 374 io.in.ready := Cat(io.out.map(_.ready)).andR 375} 376 377class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 378 val flush = Flipped(ValidIO(new Redirect())) 379 val in = Flipped(DecoupledIO(new MemExuInput())) 380 val out = DecoupledIO(new MemExuOutput()) 381} 382 383class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 384 val io = IO(new MemExeUnitIO) 385 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 386 fu.io.flush := io.flush 387 fu.io.in.valid := io.in.valid 388 io.in.ready := fu.io.in.ready 389 390 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 391 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 392 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 393 fu.io.in.bits.data.imm := io.in.bits.uop.imm 394 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 395 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 396 397 io.out.valid := fu.io.out.valid 398 fu.io.out.ready := io.out.ready 399 400 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 401 io.out.bits.data := fu.io.out.bits.res.data 402 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 403 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 404 io.out.bits.uop.fuType := io.in.bits.uop.fuType 405 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 406 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 407 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 408 409 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 410}