1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.experimental.hierarchy.{Definition, instantiable} 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility.{ClockGate, DelayN} 25import utils._ 26import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 27import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 28import xiangshan.{FPUCtrlSignals, HasXSParameter, Redirect, XSBundle, XSModule} 29import xiangshan.backend.datapath.WbConfig.{PregWB, _} 30import xiangshan.backend.fu.FuType 31import xiangshan.backend.fu.vector.Bundles.{VType, Vxrm} 32import xiangshan.backend.fu.fpu.Bundles.Frm 33 34class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 35 val flush = Flipped(ValidIO(new Redirect())) 36 val in = Flipped(DecoupledIO(new ExuInput(params))) 37 val out = DecoupledIO(new ExuOutput(params)) 38 val csrio = OptionWrapper(params.hasCSR, new CSRFileIO) 39 val fenceio = OptionWrapper(params.hasFence, new FenceIO) 40 val frm = OptionWrapper(params.needSrcFrm, Input(Frm())) 41 val vxrm = OptionWrapper(params.needSrcVxrm, Input(Vxrm())) 42 val vtype = OptionWrapper(params.writeVType, new VType) 43} 44 45class ExeUnit(val exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 46 override def shouldBeInlined: Boolean = false 47 48 lazy val module = new ExeUnitImp(this)(p, exuParams) 49} 50 51class ExeUnitImp( 52 override val wrapper: ExeUnit 53)(implicit 54 p: Parameters, exuParams: ExeUnitParams 55) extends LazyModuleImp(wrapper) with HasXSParameter{ 56 private val fuCfgs = exuParams.fuConfigs 57 58 val io = IO(new ExeUnitIO(exuParams)) 59 60 val funcUnits = fuCfgs.map(cfg => { 61 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 62 val module = cfg.fuGen(p, cfg) 63 module 64 }) 65 66 if (EnableClockGate) { 67 fuCfgs.zip(funcUnits).foreach { case (cfg, fu) => 68 val clk_en = WireInit(false.B) 69 val fuVld_en = WireInit(false.B) 70 val fuVld_en_reg = RegInit(false.B) 71 val uncer_en_reg = RegInit(false.B) 72 73 def latReal: Int = cfg.latency.latencyVal.getOrElse(0) 74 def extralat: Int = cfg.latency.extraLatencyVal.getOrElse(0) 75 76 val uncerLat = cfg.latency.uncertainLatencyVal.nonEmpty 77 val lat0 = (latReal == 0 && !uncerLat).asBool 78 val latN = (latReal > 0&& !uncerLat).asBool 79 80 81 82 val fuVldVec = (io.in.valid && latN) +: Seq.fill(latReal)(RegInit(false.B)) 83 val fuRdyVec = Seq.fill(latReal)(Wire(Bool())) :+ io.out.ready 84 85 for (i <- 0 until latReal) { 86 fuRdyVec(i) := !fuVldVec(i + 1) || fuRdyVec(i + 1) 87 } 88 89 for (i <- 1 to latReal) { 90 when(fuRdyVec(i - 1) && fuVldVec(i - 1)) { 91 fuVldVec(i) := fuVldVec(i - 1) 92 }.elsewhen(fuRdyVec(i)) { 93 fuVldVec(i) := false.B 94 } 95 } 96 fuVld_en := fuVldVec.map(v => v).reduce(_ || _) 97 fuVld_en_reg := fuVld_en 98 99 when(uncerLat.asBool && io.in.fire) { 100 uncer_en_reg := true.B 101 }.elsewhen(uncerLat.asBool && io.out.fire) { 102 uncer_en_reg := false.B 103 } 104 105 when(lat0 && io.in.fire) { 106 clk_en := true.B 107 }.elsewhen(latN && fuVld_en || fuVld_en_reg) { 108 clk_en := true.B 109 }.elsewhen(uncerLat.asBool && io.in.fire || uncer_en_reg) { 110 clk_en := true.B 111 } 112 113 if (cfg.ckAlwaysEn) { 114 clk_en := true.B 115 } 116 117 fu.clock := ClockGate(false.B, clk_en, clock) 118 XSPerfAccumulate(s"clock_gate_en_${fu.cfg.name}", clk_en) 119 } 120 } 121 122 val busy = RegInit(false.B) 123 if (exuParams.latencyCertain){ 124 busy := false.B 125 } 126 else { 127 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 128 when(io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 129 busy := false.B 130 }.elsewhen(busy && robIdx.needFlush(io.flush)) { 131 busy := false.B 132 }.elsewhen(io.out.fire) { 133 busy := false.B 134 }.elsewhen(io.in.fire) { 135 busy := true.B 136 } 137 } 138 139 exuParams.wbPortConfigs.map{ 140 x => x match { 141 case IntWB(port, priority) => assert(priority >= 0 && priority <= 2, 142 s"${exuParams.name}: WbPort must priority=0 or priority=1") 143 case VfWB (port, priority) => assert(priority >= 0 && priority <= 2, 144 s"${exuParams.name}: WbPort must priority=0 or priority=1") 145 case _ => 146 } 147 } 148 val intWbPort = exuParams.getIntWBPort 149 if (intWbPort.isDefined){ 150 val sameIntPortExuParam = backendParams.allExuParams.filter(_.getIntWBPort.isDefined) 151 .filter(_.getIntWBPort.get.port == intWbPort.get.port) 152 val samePortOneCertainOneUncertain = sameIntPortExuParam.map(_.latencyCertain).contains(true) && sameIntPortExuParam.map(_.latencyCertain).contains(false) 153 if (samePortOneCertainOneUncertain) sameIntPortExuParam.map(samePort => 154 samePort.wbPortConfigs.map( 155 x => x match { 156 case IntWB(port, priority) => { 157 if (!samePort.latencyCertain) assert(priority == sameIntPortExuParam.size - 1, 158 s"${samePort.name}: IntWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameIntPortExuParam.size - 1})") 159 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 160 } 161 case _ => 162 } 163 ) 164 ) 165 } 166 val vfWbPort = exuParams.getVfWBPort 167 if (vfWbPort.isDefined) { 168 val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined) 169 .filter(_.getVfWBPort.get.port == vfWbPort.get.port) 170 val samePortOneCertainOneUncertain = sameVfPortExuParam.map(_.latencyCertain).contains(true) && sameVfPortExuParam.map(_.latencyCertain).contains(false) 171 if (samePortOneCertainOneUncertain) sameVfPortExuParam.map(samePort => 172 samePort.wbPortConfigs.map( 173 x => x match { 174 case VfWB(port, priority) => { 175 if (!samePort.latencyCertain) assert(priority == sameVfPortExuParam.size - 1, 176 s"${samePort.name}: VfWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameVfPortExuParam.size - 1})") 177 // Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority 178 } 179 case _ => 180 } 181 ) 182 ) 183 } 184 if(backendParams.debugEn) { 185 dontTouch(io.out.ready) 186 } 187 // rob flush --> funcUnits 188 funcUnits.zipWithIndex.foreach { case (fu, i) => 189 fu.io.flush <> io.flush 190 } 191 192 def acceptCond(input: ExuInput): Seq[Bool] = { 193 input.params.fuConfigs.map(_.fuSel(input)) 194 } 195 196 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 197 198 // ExeUnit.in <---> Dispatcher.in 199 in1ToN.io.in.valid := io.in.valid && !busy 200 in1ToN.io.in.bits := io.in.bits 201 io.in.ready := !busy && in1ToN.io.in.ready 202 203 // Dispatcher.out <---> FunctionUnits 204 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 205 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 206 sink.valid := source.valid 207 source.ready := sink.ready 208 209 sink.bits.data.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 210 sink.bits.data.pc .foreach(x => x := source.bits.pc.get) 211 sink.bits.data.imm := source.bits.imm 212 sink.bits.ctrl.fuOpType := source.bits.fuOpType 213 sink.bits.ctrl.robIdx := source.bits.robIdx 214 sink.bits.ctrl.pdest := source.bits.pdest 215 sink.bits.ctrl.rfWen .foreach(x => x := source.bits.rfWen.get) 216 sink.bits.ctrl.fpWen .foreach(x => x := source.bits.fpWen.get) 217 sink.bits.ctrl.vecWen .foreach(x => x := source.bits.vecWen.get) 218 sink.bits.ctrl.flushPipe .foreach(x => x := source.bits.flushPipe.get) 219 sink.bits.ctrl.preDecode .foreach(x => x := source.bits.preDecode.get) 220 sink.bits.ctrl.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 221 sink.bits.ctrl.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 222 sink.bits.ctrl.predictInfo .foreach(x => x := source.bits.predictInfo.get) 223 sink.bits.ctrl.fpu .foreach(x => x := source.bits.fpu.get) 224 sink.bits.ctrl.vpu .foreach(x => x := source.bits.vpu.get) 225 sink.bits.perfDebugInfo := source.bits.perfDebugInfo 226 } 227 228 private val OutresVecs = funcUnits.map { fu => 229 def latDiff :Int = fu.cfg.latency.extraLatencyVal.getOrElse(0) 230 val OutresVec = fu.io.out.bits.res +: Seq.fill(latDiff)(Reg(chiselTypeOf(fu.io.out.bits.res))) 231 for (i <- 1 to latDiff) { 232 OutresVec(i) := OutresVec(i - 1) 233 } 234 OutresVec 235 } 236 OutresVecs.foreach(vec => vec.foreach(res =>dontTouch(res))) 237 238 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 239 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 240 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 241 private val fuOutresVec = OutresVecs.map(_.last) 242 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = fuOutresVec.map(_.redirect) 243 244 // Assume that one fu can only write int or fp or vec, 245 // otherwise, wenVec should be assigned to wen in fu. 246 private val fuIntWenVec = funcUnits.map(x => x.cfg.needIntWen.B && x.io.out.bits.ctrl.rfWen.getOrElse(false.B)) 247 private val fuFpWenVec = funcUnits.map(x => x.cfg.needFpWen.B && x.io.out.bits.ctrl.fpWen.getOrElse(false.B)) 248 private val fuVecWenVec = funcUnits.map(x => x.cfg.needVecWen.B && x.io.out.bits.ctrl.vecWen.getOrElse(false.B)) 249 // FunctionUnits <---> ExeUnit.out 250 io.out.valid := Cat(fuOutValidOH).orR 251 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 252 253 // select one fu's result 254 io.out.bits.data := Mux1H(fuOutValidOH, fuOutresVec.map(_.data)) 255 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.robIdx)) 256 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.pdest)) 257 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 258 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 259 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 260 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 261 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 262 io.out.bits.wflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.fpu.getOrElse(0.U.asTypeOf(new FPUCtrlSignals)).wflags))) 263 io.out.bits.vxsat.foreach(x => x := Mux1H(fuOutValidOH, fuOutresVec.map(_.vxsat.getOrElse(0.U.asTypeOf(io.out.bits.vxsat.get))))) 264 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 265 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 266 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 267 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.ctrl.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 268 269 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 270 fuio => 271 exuio <> fuio 272 fuio.exception := DelayN(exuio.exception, 2) 273 })) 274 275 io.vtype.foreach(exuio => funcUnits.foreach(fu => fu.io.vtype.foreach(fuio => exuio := fuio))) 276 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 277 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 278 io.vxrm.foreach(exuio => funcUnits.foreach(fu => fu.io.vxrm.foreach(fuio => fuio <> exuio))) 279 280 // debug info 281 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 282 io.out.bits.debug.isPerfCnt := funcUnits.map(_.io.csrio.map(_.isPerfCnt)).map(_.getOrElse(false.B)).reduce(_ || _) 283 io.out.bits.debugInfo := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.perfDebugInfo)) 284} 285 286class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 287 val in = Flipped(DecoupledIO(gen)) 288 289 val out = Vec(n, DecoupledIO(gen)) 290} 291 292class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 293 (implicit p: Parameters) 294 extends Module { 295 296 val io = IO(new DispatcherIO(gen, n)) 297 298 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 299 300 XSError(io.in.valid && PopCount(acceptVec) > 1.U, p"[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 301 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 302 303 io.out.zipWithIndex.foreach { case (out, i) => 304 out.valid := acceptVec(i) && io.in.valid 305 out.bits := io.in.bits 306 } 307 308 io.in.ready := Mux1H(acceptVec,io.out.map(_.ready)) 309} 310 311class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 312 val flush = Flipped(ValidIO(new Redirect())) 313 val in = Flipped(DecoupledIO(new MemExuInput())) 314 val out = DecoupledIO(new MemExuOutput()) 315} 316 317class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 318 val io = IO(new MemExeUnitIO) 319 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 320 fu.io.flush := io.flush 321 fu.io.in.valid := io.in.valid 322 io.in.ready := fu.io.in.ready 323 324 fu.io.in.bits.ctrl.robIdx := io.in.bits.uop.robIdx 325 fu.io.in.bits.ctrl.pdest := io.in.bits.uop.pdest 326 fu.io.in.bits.ctrl.fuOpType := io.in.bits.uop.fuOpType 327 fu.io.in.bits.data.imm := io.in.bits.uop.imm 328 fu.io.in.bits.data.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 329 fu.io.in.bits.perfDebugInfo := io.in.bits.uop.debugInfo 330 331 io.out.valid := fu.io.out.valid 332 fu.io.out.ready := io.out.ready 333 334 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 335 io.out.bits.data := fu.io.out.bits.res.data 336 io.out.bits.uop.robIdx := fu.io.out.bits.ctrl.robIdx 337 io.out.bits.uop.pdest := fu.io.out.bits.ctrl.pdest 338 io.out.bits.uop.fuType := io.in.bits.uop.fuType 339 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 340 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 341 io.out.bits.uop.debugInfo := fu.io.out.bits.perfDebugInfo 342 343 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 344}