1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend.regfile 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22 23class RfReadPort(len: Int)(implicit p: Parameters) extends XSBundle { 24 val addr = Input(UInt(PhyRegIdxWidth.W)) 25 val data = Output(UInt(len.W)) 26 override def cloneType: RfReadPort.this.type = 27 new RfReadPort(len).asInstanceOf[this.type] 28} 29 30class RfWritePort(len: Int)(implicit p: Parameters) extends XSBundle { 31 val wen = Input(Bool()) 32 val addr = Input(UInt(PhyRegIdxWidth.W)) 33 val data = Input(UInt(len.W)) 34 override def cloneType: RfWritePort.this.type = 35 new RfWritePort(len).asInstanceOf[this.type] 36} 37 38class Regfile 39( 40 numReadPorts: Int, 41 numWirtePorts: Int, 42 hasZero: Boolean, 43 len: Int 44)(implicit p: Parameters) extends XSModule { 45 val io = IO(new Bundle() { 46 val readPorts = Vec(numReadPorts, new RfReadPort(len)) 47 val writePorts = Vec(numWirtePorts, new RfWritePort(len)) 48 val debug_rports = Vec(32, new RfReadPort(len)) 49 }) 50 51 println("Regfile: size:" + NRPhyRegs + " read: " + numReadPorts + "write: " + numWirtePorts) 52 53 val useBlackBox = false 54 if (!useBlackBox) { 55 val mem = Reg(Vec(NRPhyRegs, UInt(len.W))) 56 for (r <- io.readPorts) { 57 val rdata = if (hasZero) Mux(r.addr === 0.U, 0.U, mem(r.addr)) else mem(r.addr) 58 r.data := RegNext(rdata) 59 } 60 for (w <- io.writePorts) { 61 when(w.wen) { 62 mem(w.addr) := w.data 63 } 64 } 65 66 for (rport <- io.debug_rports) { 67 val zero_rdata = Mux(rport.addr === 0.U, 0.U, mem(rport.addr)) 68 rport.data := (if (hasZero) zero_rdata else mem(rport.addr)) 69 } 70 } else { 71 72 val regfile = Module(new regfile_160x64_10w16r_sim) 73 74 regfile.io.clk := this.clock 75 regfile.io.gpr := hasZero.B 76 77 regfile.io.wen0 := io.writePorts(0).wen 78 regfile.io.waddr0 := io.writePorts(0).addr 79 regfile.io.wdata0 := io.writePorts(0).data 80 81 regfile.io.wen1 := io.writePorts(1).wen 82 regfile.io.waddr1 := io.writePorts(1).addr 83 regfile.io.wdata1 := io.writePorts(1).data 84 85 regfile.io.wen2 := io.writePorts(2).wen 86 regfile.io.waddr2 := io.writePorts(2).addr 87 regfile.io.wdata2 := io.writePorts(2).data 88 89 regfile.io.wen3 := io.writePorts(3).wen 90 regfile.io.waddr3 := io.writePorts(3).addr 91 regfile.io.wdata3 := io.writePorts(3).data 92 93 regfile.io.wen4 := io.writePorts(4).wen 94 regfile.io.waddr4 := io.writePorts(4).addr 95 regfile.io.wdata4 := io.writePorts(4).data 96 97 regfile.io.wen5 := io.writePorts(5).wen 98 regfile.io.waddr5 := io.writePorts(5).addr 99 regfile.io.wdata5 := io.writePorts(5).data 100 101 regfile.io.wen6 := io.writePorts(6).wen 102 regfile.io.waddr6 := io.writePorts(6).addr 103 regfile.io.wdata6 := io.writePorts(6).data 104 105 regfile.io.wen7 := io.writePorts(7).wen 106 regfile.io.waddr7 := io.writePorts(7).addr 107 regfile.io.wdata7 := io.writePorts(7).data 108 109 regfile.io.wen8 := false.B //io.writePorts(8).wen 110 regfile.io.waddr8 := DontCare //io.writePorts(8).addr 111 regfile.io.wdata8 := DontCare //io.writePorts(8).data 112 113 regfile.io.wen9 := false.B //io.writePorts(9).wen 114 regfile.io.waddr9 := DontCare //io.writePorts(9).addr 115 regfile.io.wdata9 := DontCare //io.writePorts(9).data 116 117 118 regfile.io.raddr0 := io.readPorts(0).addr 119 regfile.io.raddr1 := io.readPorts(1).addr 120 regfile.io.raddr2 := io.readPorts(2).addr 121 regfile.io.raddr3 := io.readPorts(3).addr 122 regfile.io.raddr4 := io.readPorts(4).addr 123 regfile.io.raddr5 := io.readPorts(5).addr 124 regfile.io.raddr6 := io.readPorts(6).addr 125 regfile.io.raddr7 := io.readPorts(7).addr 126 regfile.io.raddr8 := io.readPorts(8).addr 127 regfile.io.raddr9 := io.readPorts(9).addr 128 regfile.io.raddr10 := io.readPorts(10).addr 129 regfile.io.raddr11 := io.readPorts(11).addr 130 regfile.io.raddr12 := io.readPorts(12).addr 131 regfile.io.raddr13 := io.readPorts(13).addr 132 regfile.io.raddr14 := DontCare //io.readPorts(14).addr 133 regfile.io.raddr15 := DontCare //io.readPorts(15).addr 134 135 io.readPorts(0).data := regfile.io.rdata0 136 io.readPorts(1).data := regfile.io.rdata1 137 io.readPorts(2).data := regfile.io.rdata2 138 io.readPorts(3).data := regfile.io.rdata3 139 io.readPorts(4).data := regfile.io.rdata4 140 io.readPorts(5).data := regfile.io.rdata5 141 io.readPorts(6).data := regfile.io.rdata6 142 io.readPorts(7).data := regfile.io.rdata7 143 io.readPorts(8).data := regfile.io.rdata8 144 io.readPorts(9).data := regfile.io.rdata9 145 io.readPorts(10).data := regfile.io.rdata10 146 io.readPorts(11).data := regfile.io.rdata11 147 io.readPorts(12).data := regfile.io.rdata12 148 io.readPorts(13).data := regfile.io.rdata13 149 150 io.debug_rports := DontCare 151 } 152 153} 154 155class regfile_160x64_10w16r_sim extends BlackBox with HasBlackBoxResource { 156 157 val io = IO(new Bundle{ 158 val clk = Input(Clock()) 159 val gpr = Input(Bool()) 160 161 // write 162 val wen0, wen1, wen2, wen3, wen4, wen5, wen6, wen7, wen8, wen9 = Input(Bool()) 163 val waddr0, waddr1, waddr2, waddr3, waddr4, waddr5, waddr6, waddr7, waddr8, waddr9 = Input(UInt(8.W)) 164 val wdata0, wdata1, wdata2, wdata3, wdata4, wdata5, wdata6, wdata7, wdata8, wdata9 = Input(UInt(64.W)) 165 166 // read 167 val raddr0, raddr1, raddr2, raddr3, raddr4, raddr5, raddr6, raddr7 = Input(UInt(8.W)) 168 val raddr8, raddr9, raddr10, raddr11, raddr12, raddr13, raddr14, raddr15 = Input(UInt(8.W)) 169 val rdata0, rdata1, rdata2, rdata3, rdata4, rdata5, rdata6, rdata7 = Output(UInt(64.W)) 170 val rdata8, rdata9, rdata10, rdata11, rdata12, rdata13, rdata14, rdata15 = Output(UInt(64.W)) 171 }) 172 173 val vsrc = "/vsrc/regfile_160x64_10w16r_sim.v" 174 println(s"Regfile: Using verilog source at: $vsrc") 175 setResource(vsrc) 176 177} 178 179