1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend.issue 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23 24class WakeupQueue(number: Int)(implicit p: Parameters) extends XSModule { 25 val io = IO(new Bundle { 26 val in = Flipped(ValidIO(new MicroOp)) 27 val out = ValidIO(new MicroOp) 28 val redirect = Flipped(ValidIO(new Redirect)) 29 val flush = Input(Bool()) 30 }) 31 if (number < 0) { 32 io.out.valid := false.B 33 io.out.bits := DontCare 34 } else if(number == 0) { 35 io.in <> io.out 36 io.out.valid := io.in.valid 37 // NOTE: no delay bypass don't care redirect 38 } else { 39 val queue = Seq.fill(number)(RegInit(0.U.asTypeOf(new Bundle{ 40 val valid = Bool() 41 val bits = new MicroOp 42 }))) 43 queue(0).valid := io.in.valid && !io.in.bits.roqIdx.needFlush(io.redirect, io.flush) 44 queue(0).bits := io.in.bits 45 (0 until (number-1)).map{i => 46 queue(i+1) := queue(i) 47 queue(i+1).valid := queue(i).valid && !queue(i).bits.roqIdx.needFlush(io.redirect, io.flush) 48 } 49 io.out.valid := queue(number-1).valid 50 io.out.bits := queue(number-1).bits 51 for (i <- 0 until number) { 52 XSDebug(queue(i).valid, p"BPQue(${i.U}): pc:${Hexadecimal(queue(i).bits.cf.pc)} roqIdx:${queue(i).bits.roqIdx}" + 53 p" pdest:${queue(i).bits.pdest} rfWen:${queue(i).bits.ctrl.rfWen} fpWen${queue(i).bits.ctrl.fpWen}\n") 54 } 55 } 56} 57