1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.fu.vector.Bundles.VType 33import yunsuan.VpermType 34 35import scala.collection.Seq 36 37trait VectorConstants { 38 val MAX_VLMUL = 8 39 val FP_TMP_REG_MV = 32 40 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 41 val VECTOR_VCONFIG = 39 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59/** 60 * @author zly 61 */ 62class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 63 val io = IO(new DecodeUnitCompIO) 64 65 val maxUopSize = MaxUopSize 66 //input bits 67 val staticInst = Wire(new StaticInst) 68 69 staticInst := io.enq.staticInst 70 71 val src1 = Cat(0.U(1.W), staticInst.instr(19, 15)) 72 val src2 = Cat(0.U(1.W), staticInst.instr(24, 20)) 73 val dest = Cat(0.U(1.W), staticInst.instr(11, 7)) 74 75 //output bits 76 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 77 val validToRename = Wire(Vec(RenameWidth, Bool())) 78 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 79 val complexNum = Wire(UInt(3.W)) 80 81 //output of DecodeUnit 82 val decodedInsts_u = Wire(new DecodedInst) 83 val isVset_u = Wire(Bool()) 84 85 //pre decode 86 val simple = Module(new DecodeUnit) 87 simple.io.enq.ctrlFlow := staticInst 88 simple.io.enq.vtype := io.vtype 89 simple.io.csrCtrl := io.csrCtrl 90 decodedInsts_u := simple.io.deq.decodedInst 91 isVset_u := simple.io.deq.decodedInst.isVset 92 when(isVset_u) { 93 when(dest === 0.U && src1 === 0.U) { 94 decodedInsts_u.fuOpType := VSETOpType.convert2oldvl(simple.io.deq.decodedInst.fuOpType) 95 }.elsewhen(src1 === 0.U) { 96 decodedInsts_u.fuOpType := VSETOpType.convert2vlmax(simple.io.deq.decodedInst.fuOpType) 97 } 98 } 99 //Type of uop Div 100 val typeOfDiv = decodedInsts_u.uopDivType 101 102 //LMUL 103 val lmul = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 104 "b001".U -> 2.U, 105 "b010".U -> 4.U, 106 "b011".U -> 8.U 107 )) 108 val numOfUopVslide = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize+1).W), Array( 109 "b001".U -> 3.U, 110 "b010".U -> 10.U, 111 "b011".U -> 36.U 112 )) 113 //number of uop 114 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxUopSize+1).W), Array( 115 UopDivType.VEC_0XV -> 2.U, 116 UopDivType.DIR -> Mux(dest =/= 0.U, 2.U, 117 Mux(src1 =/= 0.U, 1.U, 118 Mux(VSETOpType.isVsetvl(decodedInsts_u.fuOpType), 2.U, 1.U))), 119 UopDivType.VEC_VVV -> lmul, 120 UopDivType.VEC_EXT2 -> lmul, 121 UopDivType.VEC_EXT4 -> lmul, 122 UopDivType.VEC_EXT8 -> lmul, 123 UopDivType.VEC_VVM -> lmul, 124 UopDivType.VEC_VXM -> (lmul +& 1.U), 125 UopDivType.VEC_VXV -> (lmul +& 1.U), 126 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 127 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 128 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 129 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 130 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 131 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 132 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 133 UopDivType.VEC_FSLIDE1UP -> lmul, 134 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 135 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 136 UopDivType.VEC_VRED -> lmul, 137 UopDivType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 138 UopDivType.VEC_ISLIDEUP -> numOfUopVslide, 139 UopDivType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 140 UopDivType.VEC_ISLIDEDOWN -> numOfUopVslide, 141 UopDivType.VEC_M0X -> (lmul +& 1.U), 142 UopDivType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 143 UopDivType.VEC_M0X_VFIRST -> 2.U, 144 )) 145 146 //uop div up to maxUopSize 147 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 148 csBundle.map { case dst => 149 dst := decodedInsts_u 150 dst.firstUop := false.B 151 dst.lastUop := false.B 152 } 153 154 csBundle(0).firstUop := true.B 155 csBundle(numOfUop - 1.U).lastUop := true.B 156 157 switch(typeOfDiv) { 158 is(UopDivType.DIR) { 159 when(isVset_u) { 160 when(dest =/= 0.U) { 161 csBundle(0).fuType := FuType.vsetiwi.U 162 csBundle(0).fuOpType := VSETOpType.convert2uvsetvl(decodedInsts_u.fuOpType) 163 csBundle(0).flushPipe := false.B 164 csBundle(0).rfWen := true.B 165 csBundle(0).vecWen := false.B 166 csBundle(1).ldest := VECTOR_VCONFIG.U 167 }.elsewhen(src1 =/= 0.U) { 168 csBundle(0).ldest := VECTOR_VCONFIG.U 169 }.elsewhen(VSETOpType.isVsetvli(decodedInsts_u.fuOpType)) { 170 csBundle(0).fuType := FuType.vsetfwf.U 171 csBundle(0).srcType(0) := SrcType.vp 172 csBundle(0).lsrc(0) := VECTOR_VCONFIG.U 173 }.elsewhen(VSETOpType.isVsetvl(decodedInsts_u.fuOpType)) { 174 csBundle(0).srcType(0) := SrcType.reg 175 csBundle(0).srcType(1) := SrcType.imm 176 csBundle(0).lsrc(1) := 0.U 177 csBundle(0).ldest := FP_TMP_REG_MV.U 178 csBundle(0).fuType := FuType.i2f.U 179 csBundle(0).rfWen := false.B 180 csBundle(0).fpWen := true.B 181 csBundle(0).vecWen := false.B 182 csBundle(0).fpu.isAddSub := false.B 183 csBundle(0).fpu.typeTagIn := FPU.D 184 csBundle(0).fpu.typeTagOut := FPU.D 185 csBundle(0).fpu.fromInt := true.B 186 csBundle(0).fpu.wflags := false.B 187 csBundle(0).fpu.fpWen := true.B 188 csBundle(0).fpu.div := false.B 189 csBundle(0).fpu.sqrt := false.B 190 csBundle(0).fpu.fcvt := false.B 191 csBundle(0).flushPipe := false.B 192 csBundle(1).fuType := FuType.vsetfwf.U 193 csBundle(1).srcType(0) := SrcType.vp 194 csBundle(1).lsrc(0) := VECTOR_VCONFIG.U 195 csBundle(1).srcType(1) := SrcType.fp 196 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 197 csBundle(1).ldest := VECTOR_VCONFIG.U 198 } 199 } 200 } 201 is(UopDivType.VEC_VVV) { 202 for (i <- 0 until MAX_VLMUL) { 203 csBundle(i).lsrc(0) := src1 + i.U 204 csBundle(i).lsrc(1) := src2 + i.U 205 csBundle(i).lsrc(2) := dest + i.U 206 csBundle(i).ldest := dest + i.U 207 csBundle(i).uopIdx := i.U 208 } 209 } 210 is(UopDivType.VEC_EXT2) { 211 for (i <- 0 until MAX_VLMUL / 2) { 212 csBundle(2 * i).lsrc(1) := src2 + i.U 213 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 214 csBundle(2 * i).ldest := dest + (2 * i).U 215 csBundle(2 * i).uopIdx := (2 * i).U 216 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 217 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 218 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 219 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 220 } 221 } 222 is(UopDivType.VEC_EXT4) { 223 for (i <- 0 until MAX_VLMUL / 4) { 224 csBundle(4 * i).lsrc(1) := src2 + i.U 225 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 226 csBundle(4 * i).ldest := dest + (4 * i).U 227 csBundle(4 * i).uopIdx := (4 * i).U 228 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 229 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 230 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 231 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 232 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 233 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 234 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 235 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 236 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 237 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 238 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 239 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 240 } 241 } 242 is(UopDivType.VEC_EXT8) { 243 for (i <- 0 until MAX_VLMUL) { 244 csBundle(i).lsrc(1) := src2 245 csBundle(i).lsrc(2) := dest + i.U 246 csBundle(i).ldest := dest + i.U 247 csBundle(i).uopIdx := i.U 248 } 249 } 250 is(UopDivType.VEC_0XV) { 251 /* 252 FMV.D.X 253 */ 254 csBundle(0).srcType(0) := SrcType.reg 255 csBundle(0).srcType(1) := SrcType.imm 256 csBundle(0).lsrc(1) := 0.U 257 csBundle(0).ldest := FP_TMP_REG_MV.U 258 csBundle(0).fuType := FuType.i2f.U 259 csBundle(0).rfWen := false.B 260 csBundle(0).fpWen := true.B 261 csBundle(0).vecWen := false.B 262 csBundle(0).fpu.isAddSub := false.B 263 csBundle(0).fpu.typeTagIn := FPU.D 264 csBundle(0).fpu.typeTagOut := FPU.D 265 csBundle(0).fpu.fromInt := true.B 266 csBundle(0).fpu.wflags := false.B 267 csBundle(0).fpu.fpWen := true.B 268 csBundle(0).fpu.div := false.B 269 csBundle(0).fpu.sqrt := false.B 270 csBundle(0).fpu.fcvt := false.B 271 /* 272 vfmv.s.f 273 */ 274 csBundle(1).srcType(0) := SrcType.fp 275 csBundle(1).srcType(1) := SrcType.vp 276 csBundle(1).srcType(2) := SrcType.vp 277 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 278 csBundle(1).lsrc(1) := 0.U 279 csBundle(1).lsrc(2) := dest 280 csBundle(1).ldest := dest 281 csBundle(1).fuType := FuType.vppu.U 282 csBundle(1).fuOpType := VpermType.vfmv_s_f 283 csBundle(1).rfWen := false.B 284 csBundle(1).fpWen := false.B 285 csBundle(1).vecWen := true.B 286 } 287 is(UopDivType.VEC_VXV) { 288 /* 289 FMV.D.X 290 */ 291 csBundle(0).srcType(0) := SrcType.reg 292 csBundle(0).srcType(1) := SrcType.imm 293 csBundle(0).lsrc(1) := 0.U 294 csBundle(0).ldest := FP_TMP_REG_MV.U 295 csBundle(0).fuType := FuType.i2f.U 296 csBundle(0).rfWen := false.B 297 csBundle(0).fpWen := true.B 298 csBundle(0).vecWen := false.B 299 csBundle(0).fpu.isAddSub := false.B 300 csBundle(0).fpu.typeTagIn := FPU.D 301 csBundle(0).fpu.typeTagOut := FPU.D 302 csBundle(0).fpu.fromInt := true.B 303 csBundle(0).fpu.wflags := false.B 304 csBundle(0).fpu.fpWen := true.B 305 csBundle(0).fpu.div := false.B 306 csBundle(0).fpu.sqrt := false.B 307 csBundle(0).fpu.fcvt := false.B 308 /* 309 LMUL 310 */ 311 for (i <- 0 until MAX_VLMUL) { 312 csBundle(i + 1).srcType(0) := SrcType.fp 313 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 314 csBundle(i + 1).lsrc(1) := src2 + i.U 315 csBundle(i + 1).lsrc(2) := dest + i.U 316 csBundle(i + 1).ldest := dest + i.U 317 csBundle(i + 1).uopIdx := i.U 318 } 319 } 320 is(UopDivType.VEC_VVW) { 321 for (i <- 0 until MAX_VLMUL / 2) { 322 csBundle(2 * i).lsrc(0) := src1 + i.U 323 csBundle(2 * i).lsrc(1) := src2 + i.U 324 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 325 csBundle(2 * i).ldest := dest + (2 * i).U 326 csBundle(2 * i).uopIdx := (2 * i).U 327 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 328 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 329 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 330 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 331 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 332 } 333 } 334 is(UopDivType.VEC_WVW) { 335 for (i <- 0 until MAX_VLMUL / 2) { 336 csBundle(2 * i).lsrc(0) := src1 + i.U 337 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 338 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 339 csBundle(2 * i).ldest := dest + (2 * i).U 340 csBundle(2 * i).uopIdx := (2 * i).U 341 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 342 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 343 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 344 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 345 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 346 } 347 } 348 is(UopDivType.VEC_VXW) { 349 /* 350 FMV.D.X 351 */ 352 csBundle(0).srcType(0) := SrcType.reg 353 csBundle(0).srcType(1) := SrcType.imm 354 csBundle(0).lsrc(1) := 0.U 355 csBundle(0).ldest := FP_TMP_REG_MV.U 356 csBundle(0).fuType := FuType.i2f.U 357 csBundle(0).rfWen := false.B 358 csBundle(0).fpWen := true.B 359 csBundle(0).vecWen := false.B 360 csBundle(0).fpu.isAddSub := false.B 361 csBundle(0).fpu.typeTagIn := FPU.D 362 csBundle(0).fpu.typeTagOut := FPU.D 363 csBundle(0).fpu.fromInt := true.B 364 csBundle(0).fpu.wflags := false.B 365 csBundle(0).fpu.fpWen := true.B 366 csBundle(0).fpu.div := false.B 367 csBundle(0).fpu.sqrt := false.B 368 csBundle(0).fpu.fcvt := false.B 369 370 for (i <- 0 until MAX_VLMUL / 2) { 371 csBundle(2 * i + 1).srcType(0) := SrcType.fp 372 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 373 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 374 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 375 csBundle(2 * i + 1).ldest := dest + (2 * i).U 376 csBundle(2 * i + 1).uopIdx := (2 * i).U 377 csBundle(2 * i + 2).srcType(0) := SrcType.fp 378 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 379 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 380 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 381 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 382 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 383 } 384 } 385 is(UopDivType.VEC_WXW) { 386 /* 387 FMV.D.X 388 */ 389 csBundle(0).srcType(0) := SrcType.reg 390 csBundle(0).srcType(1) := SrcType.imm 391 csBundle(0).lsrc(1) := 0.U 392 csBundle(0).ldest := FP_TMP_REG_MV.U 393 csBundle(0).fuType := FuType.i2f.U 394 csBundle(0).rfWen := false.B 395 csBundle(0).fpWen := true.B 396 csBundle(0).vecWen := false.B 397 csBundle(0).fpu.isAddSub := false.B 398 csBundle(0).fpu.typeTagIn := FPU.D 399 csBundle(0).fpu.typeTagOut := FPU.D 400 csBundle(0).fpu.fromInt := true.B 401 csBundle(0).fpu.wflags := false.B 402 csBundle(0).fpu.fpWen := true.B 403 csBundle(0).fpu.div := false.B 404 csBundle(0).fpu.sqrt := false.B 405 csBundle(0).fpu.fcvt := false.B 406 407 for (i <- 0 until MAX_VLMUL / 2) { 408 csBundle(2 * i + 1).srcType(0) := SrcType.fp 409 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 410 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 411 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 412 csBundle(2 * i + 1).ldest := dest + (2 * i).U 413 csBundle(2 * i + 1).uopIdx := (2 * i).U 414 csBundle(2 * i + 2).srcType(0) := SrcType.fp 415 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 416 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 417 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 418 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 419 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 420 } 421 } 422 is(UopDivType.VEC_WVV) { 423 for (i <- 0 until MAX_VLMUL / 2) { 424 425 csBundle(2 * i).lsrc(0) := src1 + i.U 426 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 427 csBundle(2 * i).lsrc(2) := dest + i.U 428 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 429 csBundle(2 * i).uopIdx := (2 * i).U 430 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 431 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 432 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 433 csBundle(2 * i + 1).ldest := dest + i.U 434 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 435 } 436 } 437 is(UopDivType.VEC_WXV) { 438 /* 439 FMV.D.X 440 */ 441 csBundle(0).srcType(0) := SrcType.reg 442 csBundle(0).srcType(1) := SrcType.imm 443 csBundle(0).lsrc(1) := 0.U 444 csBundle(0).ldest := FP_TMP_REG_MV.U 445 csBundle(0).fuType := FuType.i2f.U 446 csBundle(0).rfWen := false.B 447 csBundle(0).fpWen := true.B 448 csBundle(0).vecWen := false.B 449 csBundle(0).fpu.isAddSub := false.B 450 csBundle(0).fpu.typeTagIn := FPU.D 451 csBundle(0).fpu.typeTagOut := FPU.D 452 csBundle(0).fpu.fromInt := true.B 453 csBundle(0).fpu.wflags := false.B 454 csBundle(0).fpu.fpWen := true.B 455 csBundle(0).fpu.div := false.B 456 csBundle(0).fpu.sqrt := false.B 457 csBundle(0).fpu.fcvt := false.B 458 459 for (i <- 0 until MAX_VLMUL / 2) { 460 csBundle(2 * i + 1).srcType(0) := SrcType.fp 461 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 462 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 463 csBundle(2 * i + 1).lsrc(2) := dest + i.U 464 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 465 csBundle(2 * i + 1).uopIdx := (2 * i).U 466 csBundle(2 * i + 2).srcType(0) := SrcType.fp 467 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 468 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 469 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 470 csBundle(2 * i + 2).ldest := dest + i.U 471 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 472 } 473 } 474 is(UopDivType.VEC_VVM) { 475 csBundle(0).lsrc(2) := dest 476 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 477 csBundle(0).uopIdx := 0.U 478 for(i <- 1 until MAX_VLMUL) { 479 csBundle(i).lsrc(0) := src1 + i.U 480 csBundle(i).lsrc(1) := src2 + i.U 481 csBundle(i).lsrc(2) := VECTOR_TMP_REG_LMUL.U 482 csBundle(i).ldest := VECTOR_TMP_REG_LMUL.U 483 csBundle(i).uopIdx := i.U 484 } 485 csBundle(numOfUop - 1.U).ldest := dest 486 } 487 is(UopDivType.VEC_VXM) { 488 /* 489 FMV.D.X 490 */ 491 csBundle(0).srcType(0) := SrcType.reg 492 csBundle(0).srcType(1) := SrcType.imm 493 csBundle(0).lsrc(1) := 0.U 494 csBundle(0).ldest := FP_TMP_REG_MV.U 495 csBundle(0).fuType := FuType.i2f.U 496 csBundle(0).rfWen := false.B 497 csBundle(0).fpWen := true.B 498 csBundle(0).vecWen := false.B 499 csBundle(0).fpu.isAddSub := false.B 500 csBundle(0).fpu.typeTagIn := FPU.D 501 csBundle(0).fpu.typeTagOut := FPU.D 502 csBundle(0).fpu.fromInt := true.B 503 csBundle(0).fpu.wflags := false.B 504 csBundle(0).fpu.fpWen := true.B 505 csBundle(0).fpu.div := false.B 506 csBundle(0).fpu.sqrt := false.B 507 csBundle(0).fpu.fcvt := false.B 508 //LMUL 509 csBundle(1).srcType(0) := SrcType.fp 510 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 511 csBundle(1).lsrc(2) := dest 512 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 513 csBundle(1).uopIdx := 0.U 514 for (i <- 1 until MAX_VLMUL) { 515 csBundle(i + 1).srcType(0) := SrcType.fp 516 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 517 csBundle(i + 1).lsrc(1) := src2 + i.U 518 csBundle(i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 519 csBundle(i + 1).ldest := VECTOR_TMP_REG_LMUL.U 520 csBundle(i + 1).uopIdx := i.U 521 } 522 csBundle(numOfUop - 1.U).ldest := dest 523 } 524 is(UopDivType.VEC_SLIDE1UP) { 525 /* 526 FMV.D.X 527 */ 528 csBundle(0).srcType(0) := SrcType.reg 529 csBundle(0).srcType(1) := SrcType.imm 530 csBundle(0).lsrc(1) := 0.U 531 csBundle(0).ldest := FP_TMP_REG_MV.U 532 csBundle(0).fuType := FuType.i2f.U 533 csBundle(0).rfWen := false.B 534 csBundle(0).fpWen := true.B 535 csBundle(0).vecWen := false.B 536 csBundle(0).fpu.isAddSub := false.B 537 csBundle(0).fpu.typeTagIn := FPU.D 538 csBundle(0).fpu.typeTagOut := FPU.D 539 csBundle(0).fpu.fromInt := true.B 540 csBundle(0).fpu.wflags := false.B 541 csBundle(0).fpu.fpWen := true.B 542 csBundle(0).fpu.div := false.B 543 csBundle(0).fpu.sqrt := false.B 544 csBundle(0).fpu.fcvt := false.B 545 //LMUL 546 csBundle(1).srcType(0) := SrcType.fp 547 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 548 csBundle(1).lsrc(2) := dest 549 csBundle(1).ldest := dest 550 csBundle(1).uopIdx := 0.U 551 for (i <- 1 until MAX_VLMUL) { 552 csBundle(i + 1).srcType(0) := SrcType.vp 553 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 554 csBundle(i + 1).lsrc(1) := src2 + i.U 555 csBundle(i + 1).lsrc(2) := dest + i.U 556 csBundle(i + 1).ldest := dest + i.U 557 csBundle(i + 1).uopIdx := i.U 558 } 559 } 560 is(UopDivType.VEC_FSLIDE1UP) { 561 //LMUL 562 csBundle(0).srcType(0) := SrcType.fp 563 csBundle(0).lsrc(0) := src1 564 csBundle(0).lsrc(1) := src2 565 csBundle(0).lsrc(2) := dest 566 csBundle(0).ldest := dest 567 csBundle(0).uopIdx := 0.U 568 for (i <- 1 until MAX_VLMUL) { 569 csBundle(i).srcType(0) := SrcType.vp 570 csBundle(i).lsrc(0) := src2 + (i - 1).U 571 csBundle(i).lsrc(1) := src2 + i.U 572 csBundle(i).lsrc(2) := dest + i.U 573 csBundle(i).ldest := dest + i.U 574 csBundle(i).uopIdx := i.U 575 } 576 } 577 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 578 /* 579 FMV.D.X 580 */ 581 csBundle(0).srcType(0) := SrcType.reg 582 csBundle(0).srcType(1) := SrcType.imm 583 csBundle(0).lsrc(1) := 0.U 584 csBundle(0).ldest := FP_TMP_REG_MV.U 585 csBundle(0).fuType := FuType.i2f.U 586 csBundle(0).rfWen := false.B 587 csBundle(0).fpWen := true.B 588 csBundle(0).vecWen := false.B 589 csBundle(0).fpu.isAddSub := false.B 590 csBundle(0).fpu.typeTagIn := FPU.D 591 csBundle(0).fpu.typeTagOut := FPU.D 592 csBundle(0).fpu.fromInt := true.B 593 csBundle(0).fpu.wflags := false.B 594 csBundle(0).fpu.fpWen := true.B 595 csBundle(0).fpu.div := false.B 596 csBundle(0).fpu.sqrt := false.B 597 csBundle(0).fpu.fcvt := false.B 598 //LMUL 599 for (i <- 0 until MAX_VLMUL) { 600 csBundle(2 * i + 1).srcType(0) := SrcType.vp 601 csBundle(2 * i + 1).srcType(1) := SrcType.vp 602 csBundle(2 * i + 1).lsrc(0) := src2 + (i+1).U 603 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 604 csBundle(2 * i + 1).lsrc(2) := dest + i.U 605 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 606 csBundle(2 * i + 1).uopIdx := (2 * i).U 607 if (2 * i + 2 < MAX_VLMUL * 2 ){ 608 csBundle(2 * i + 2).srcType(0) := SrcType.fp 609 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 610 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 611 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 612 csBundle(2 * i + 2).ldest := dest + i.U 613 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 614 } 615 } 616 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 617 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 618 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 619 } 620 is(UopDivType.VEC_FSLIDE1DOWN) { 621 //LMUL 622 for (i <- 0 until MAX_VLMUL) { 623 csBundle(2 * i).srcType(0) := SrcType.vp 624 csBundle(2 * i).srcType(1) := SrcType.vp 625 csBundle(2 * i).lsrc(0) := src2 + (i+1).U 626 csBundle(2 * i).lsrc(1) := src2 + i.U 627 csBundle(2 * i).lsrc(2) := dest + i.U 628 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 629 csBundle(2 * i).uopIdx := (2 * i).U 630 csBundle(2 * i + 1).srcType(0) := SrcType.fp 631 csBundle(2 * i + 1).lsrc(0) := src1 632 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 633 csBundle(2 * i + 1).ldest := dest + i.U 634 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 635 } 636 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 637 csBundle(numOfUop - 1.U).lsrc(0) := src1 638 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 639 } 640 is(UopDivType.VEC_VRED) { 641 when(simple.io.enq.vtype.vlmul === "b001".U){ 642 csBundle(0).srcType(2) := SrcType.DC 643 csBundle(0).lsrc(0) := src2 + 1.U 644 csBundle(0).lsrc(1) := src2 645 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 646 csBundle(0).uopIdx := 0.U 647 } 648 when(simple.io.enq.vtype.vlmul === "b010".U) { 649 csBundle(0).srcType(2) := SrcType.DC 650 csBundle(0).lsrc(0) := src2 + 1.U 651 csBundle(0).lsrc(1) := src2 652 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 653 csBundle(0).uopIdx := 0.U 654 655 csBundle(1).srcType(2) := SrcType.DC 656 csBundle(1).lsrc(0) := src2 + 3.U 657 csBundle(1).lsrc(1) := src2 + 2.U 658 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL+1).U 659 csBundle(1).uopIdx := 1.U 660 661 csBundle(2).srcType(2) := SrcType.DC 662 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 663 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 664 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL+2).U 665 csBundle(2).uopIdx := 2.U 666 } 667 when(simple.io.enq.vtype.vlmul === "b011".U) { 668 for(i <- 0 until MAX_VLMUL){ 669 if(i < MAX_VLMUL - MAX_VLMUL/2){ 670 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 671 csBundle(i).lsrc(1) := src2 + (i * 2).U 672 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 673 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 674 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 675 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 676 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 677 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 678 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 679 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 680 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 681 } 682 csBundle(i).srcType(2) := SrcType.DC 683 csBundle(i).uopIdx := i.U 684 } 685 } 686 when (simple.io.enq.vtype.vlmul.orR()){ 687 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 688 csBundle(numOfUop - 1.U).lsrc(0) := src1 689 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 690 csBundle(numOfUop - 1.U).lsrc(2) := dest 691 csBundle(numOfUop - 1.U).ldest := dest 692 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 693 } 694 } 695 696 is(UopDivType.VEC_SLIDEUP) { 697 // FMV.D.X 698 csBundle(0).srcType(0) := SrcType.reg 699 csBundle(0).srcType(1) := SrcType.imm 700 csBundle(0).lsrc(1) := 0.U 701 csBundle(0).ldest := FP_TMP_REG_MV.U 702 csBundle(0).fuType := FuType.i2f.U 703 csBundle(0).rfWen := false.B 704 csBundle(0).fpWen := true.B 705 csBundle(0).vecWen := false.B 706 csBundle(0).fpu.isAddSub := false.B 707 csBundle(0).fpu.typeTagIn := FPU.D 708 csBundle(0).fpu.typeTagOut := FPU.D 709 csBundle(0).fpu.fromInt := true.B 710 csBundle(0).fpu.wflags := false.B 711 csBundle(0).fpu.fpWen := true.B 712 csBundle(0).fpu.div := false.B 713 csBundle(0).fpu.sqrt := false.B 714 csBundle(0).fpu.fcvt := false.B 715 // LMUL 716 for(i <- 0 until MAX_VLMUL) 717 for(j <- 0 to i){ 718 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 719 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 720 csBundle(i*(i+1)/2+j+1).srcType(0) := SrcType.fp 721 csBundle(i*(i+1)/2+j+1).lsrc(0) := FP_TMP_REG_MV.U 722 csBundle(i*(i+1)/2+j+1).lsrc(1) := src2 + j.U 723 csBundle(i*(i+1)/2+j+1).lsrc(2) := old_vd 724 csBundle(i*(i+1)/2+j+1).ldest := vd 725 csBundle(i*(i+1)/2+j+1).uopIdx := (i*(i+1)/2+j).U 726 } 727 } 728 729 is(UopDivType.VEC_ISLIDEUP) { 730 // LMUL 731 for(i <- 0 until MAX_VLMUL) 732 for(j <- 0 to i){ 733 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 734 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 735 csBundle(i*(i+1)/2+j).lsrc(1) := src2 + j.U 736 csBundle(i*(i+1)/2+j).lsrc(2) := old_vd 737 csBundle(i*(i+1)/2+j).ldest := vd 738 csBundle(i*(i+1)/2+j).uopIdx := (i*(i+1)/2+j).U 739 } 740 } 741 742 is(UopDivType.VEC_SLIDEDOWN) { 743 // FMV.D.X 744 csBundle(0).srcType(0) := SrcType.reg 745 csBundle(0).srcType(1) := SrcType.imm 746 csBundle(0).lsrc(1) := 0.U 747 csBundle(0).ldest := FP_TMP_REG_MV.U 748 csBundle(0).fuType := FuType.i2f.U 749 csBundle(0).rfWen := false.B 750 csBundle(0).fpWen := true.B 751 csBundle(0).vecWen := false.B 752 csBundle(0).fpu.isAddSub := false.B 753 csBundle(0).fpu.typeTagIn := FPU.D 754 csBundle(0).fpu.typeTagOut := FPU.D 755 csBundle(0).fpu.fromInt := true.B 756 csBundle(0).fpu.wflags := false.B 757 csBundle(0).fpu.fpWen := true.B 758 csBundle(0).fpu.div := false.B 759 csBundle(0).fpu.sqrt := false.B 760 csBundle(0).fpu.fcvt := false.B 761 // LMUL 762 for(i <- 0 until MAX_VLMUL) 763 for(j <- (0 to i).reverse){ 764 when(i.U < lmul){ 765 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 766 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 767 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).srcType(0) := SrcType.fp 768 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(0) := FP_TMP_REG_MV.U 769 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 770 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 771 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 772 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 773 } 774 } 775 } 776 777 is(UopDivType.VEC_ISLIDEDOWN) { 778 // LMUL 779 for(i <- 0 until MAX_VLMUL) 780 for(j <- (0 to i).reverse){ 781 when(i.U < lmul){ 782 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 783 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 784 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 785 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 786 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 787 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 788 } 789 } 790 } 791 792 is(UopDivType.VEC_M0X) { 793 // LMUL 794 for (i <- 0 until MAX_VLMUL) { 795 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 796 val ldest = (VECTOR_TMP_REG_LMUL + i).U 797 csBundle(i).srcType(0) := srcType0 798 csBundle(i).srcType(1) := SrcType.vp 799 csBundle(i).rfWen := false.B 800 csBundle(i).vecWen := true.B 801 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 802 csBundle(i).lsrc(1) := src2 803 // csBundle(i).lsrc(2) := dest + i.U DontCare 804 csBundle(i).ldest := ldest 805 csBundle(i).uopIdx := i.U 806 } 807 csBundle(lmul-1.U).vecWen := false.B 808 csBundle(lmul-1.U).fpWen := true.B 809 csBundle(lmul-1.U).ldest := FP_TMP_REG_MV.U 810 // FMV_X_D 811 csBundle(lmul).srcType(0) := SrcType.fp 812 csBundle(lmul).srcType(1) := SrcType.imm 813 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 814 csBundle(lmul).lsrc(1) := 0.U 815 csBundle(lmul).ldest := dest 816 csBundle(lmul).fuType := FuType.fmisc.U 817 csBundle(lmul).rfWen := true.B 818 csBundle(lmul).fpWen := false.B 819 csBundle(lmul).vecWen := false.B 820 csBundle(lmul).fpu.isAddSub := false.B 821 csBundle(lmul).fpu.typeTagIn := FPU.D 822 csBundle(lmul).fpu.typeTagOut := FPU.D 823 csBundle(lmul).fpu.fromInt := false.B 824 csBundle(lmul).fpu.wflags := false.B 825 csBundle(lmul).fpu.fpWen := false.B 826 csBundle(lmul).fpu.div := false.B 827 csBundle(lmul).fpu.sqrt := false.B 828 csBundle(lmul).fpu.fcvt := false.B 829 } 830 831 is(UopDivType.VEC_MVV) { 832 // LMUL 833 for (i <- 0 until MAX_VLMUL) { 834 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 835 csBundle(i*2+0).srcType(0) := srcType0 836 csBundle(i*2+0).srcType(1) := SrcType.vp 837 csBundle(i*2+0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 838 csBundle(i*2+0).lsrc(1) := src2 839 csBundle(i*2+0).lsrc(2) := dest + i.U 840 csBundle(i*2+0).ldest := dest + i.U 841 csBundle(i*2+0).uopIdx := (i*2+0).U 842 843 csBundle(i*2+1).srcType(0) := srcType0 844 csBundle(i*2+1).srcType(1) := SrcType.vp 845 csBundle(i*2+1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 846 csBundle(i*2+1).lsrc(1) := src2 847 // csBundle(i).lsrc(2) := dest + i.U DontCare 848 csBundle(i*2+1).ldest := (VECTOR_TMP_REG_LMUL + i).U 849 csBundle(i*2+1).uopIdx := (i*2+1).U 850 } 851 } 852 853 is(UopDivType.VEC_M0X_VFIRST) { 854 // LMUL 855 csBundle(0).rfWen := false.B 856 csBundle(0).fpWen := true.B 857 csBundle(0).ldest := FP_TMP_REG_MV.U 858 // FMV_X_D 859 csBundle(1).srcType(0) := SrcType.fp 860 csBundle(1).srcType(1) := SrcType.imm 861 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 862 csBundle(1).lsrc(1) := 0.U 863 csBundle(1).ldest := dest 864 csBundle(1).fuType := FuType.fmisc.U 865 csBundle(1).rfWen := true.B 866 csBundle(1).fpWen := false.B 867 csBundle(1).vecWen := false.B 868 csBundle(1).fpu.isAddSub := false.B 869 csBundle(1).fpu.typeTagIn := FPU.D 870 csBundle(1).fpu.typeTagOut := FPU.D 871 csBundle(1).fpu.fromInt := false.B 872 csBundle(1).fpu.wflags := false.B 873 csBundle(1).fpu.fpWen := false.B 874 csBundle(1).fpu.div := false.B 875 csBundle(1).fpu.sqrt := false.B 876 csBundle(1).fpu.fcvt := false.B 877 } 878 } 879 880 //uops dispatch 881 val normal :: ext :: Nil = Enum(2) 882 val stateReg = RegInit(normal) 883 val uopRes = RegInit(0.U) 884 885 //readyFromRename Counter 886 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 887 888 switch(stateReg) { 889 is(normal) { 890 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 891 } 892 is(ext) { 893 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 894 } 895 } 896 897 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 898 val uopResJudge = Mux(stateReg === normal, 899 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 900 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 901 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 902 903 for(i <- 0 until RenameWidth) { 904 decodedInsts(i) := MuxCase(csBundle(i), Seq( 905 (stateReg === normal) -> csBundle(i), 906 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 907 )) 908 } 909 910 911 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 912 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 913 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 914 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 915 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 916 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 917 notInfVec(0) := true.B 918 919 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 920 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 921 1.U) 922 validToRename.zipWithIndex.foreach{ 923 case(dst, i) => 924 dst := MuxCase(false.B, Seq( 925 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 926 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 927 )) 928 } 929 930 readyToIBuf.zipWithIndex.foreach { 931 case (dst, i) => 932 dst := MuxCase(true.B, Seq( 933 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 934 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 935 )) 936 } 937 938 io.deq.decodedInsts := decodedInsts 939 io.deq.isVset := isVset_u 940 io.deq.complexNum := complexNum 941 io.deq.validToRename := validToRename 942 io.deq.readyToIBuf := readyToIBuf 943 944} 945 946