xref: /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala (revision 602c81c352f33c6bbac0d52c7da77017ab7298ec) 
1package xiangshan.backend.decode.isa.bitfield
2
3import chisel3._
4
5abstract class RiscvInst(bitWidth: Int) extends Bundle {
6  val inst: UInt = UInt(bitWidth.W)
7}
8
9class Riscv32BitInst extends RiscvInst(32) {
10  def ALL     : UInt  = inst
11  def OPCODE  : UInt  = inst( 6,  2)
12  def RD      : UInt  = inst(11,  7)
13  def FUNCT3  : UInt  = inst(14, 12)
14  def RS1     : UInt  = inst(19, 15)
15  def RS2     : UInt  = inst(24, 20)
16  def FUNCT7  : UInt  = inst(31, 25)
17}
18
19trait BitFieldsI { this: Riscv32BitInst =>
20  def IMM12   : UInt  = inst(31, 20)
21}
22
23trait BitFieldsS { this: Riscv32BitInst =>
24  def IMM5    : UInt  = inst(11,  7)
25  def IMM7    : UInt  = inst(31, 25)
26}
27
28trait BitFieldsCSR { this: Riscv32BitInst =>
29  def CSRIDX  : UInt  = inst(31, 20)
30  def CSRIMM  : UInt  = inst(19, 15)
31}
32
33trait BitFieldsFp { this: Riscv32BitInst =>
34  def FD      : UInt  = inst(11,  7)
35  def FS1     : UInt  = inst(19, 15)
36  def FS2     : UInt  = inst(24, 20)
37  def FS3     : UInt  = inst(31, 27)
38  def RM      : UInt  = inst(14, 12) // round mode
39  def CONV_SGN: UInt  = inst(24, 20)
40  def FUNCT2  : UInt  = inst(26, 25)
41}
42
43trait BitFieldsVec { this: Riscv32BitInst =>
44  def VCATEGORY     : UInt  = inst(14, 12)
45  def NF            : UInt  = inst(31, 29)
46  def MEW           : UInt  = inst(28)
47  def MOP           : UInt  = inst(27, 26)
48  def VM            : UInt  = inst(25)
49  def LUMOP         : UInt  = inst(24, 20)
50  def SUMOP         : UInt  = inst(24, 20)
51  def WIDTH         : UInt  = inst(14, 12)
52  def VD            : UInt  = inst(11,  7)
53  def VS1           : UInt  = inst(19, 15)
54  def VS2           : UInt  = inst(24, 20)
55  def VS3           : UInt  = inst(11,  7)
56  def FUNCT6        : UInt  = inst(31 ,26)
57  def ZIMM_VSETVLI  : UInt  = inst(30, 20)
58  def ZIMM_VSETIVLI : UInt  = inst(29, 20)
59  def UIMM_VSETIVLI : UInt  = inst(19, 15)
60  def ZIMM_VTYPE    : UInt  = ZIMM_VSETIVLI(7, 0)
61  def IMM5_OPIVI    : UInt  = inst(19, 15)
62
63  def getInstVType : InstVType = {
64    val res = Wire(new InstVType)
65    res.vlmul := ZIMM_VSETVLI(2, 0)
66    res.vsew  := ZIMM_VSETVLI(5, 3)
67    res.vta   := ZIMM_VSETVLI(6)
68    res.vma   := ZIMM_VSETVLI(7)
69    res
70  }
71}
72
73class XSInstBitFields extends Riscv32BitInst
74  with BitFieldsI
75  with BitFieldsS
76  with BitFieldsCSR
77  with BitFieldsFp
78  with BitFieldsVec
79
80class InstVType extends Bundle {
81  val vma = Bool()
82  val vta = Bool()
83  val vsew = UInt(3.W)
84  val vlmul = UInt(3.W)
85}
86
87