1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import sifive.blocks.inclusivecache.{InclusiveCache, InclusiveCacheMicroParameters, CacheParameters} 27import xiangshan.frontend.{ICacheParameters} 28import xiangshan.backend.exu.ExuParameters 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 31import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 32 33class DefaultConfig(n: Int) extends Config((site, here, up) => { 34 case XLen => 64 35 case DebugOptionsKey => DebugOptions() 36 case SoCParamsKey => SoCParameters( 37 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 38 ) 39}) 40 41// Synthesizable minimal XiangShan 42// * It is still an out-of-order, super-scalaer arch 43// * L1 cache included 44// * L2 cache NOT included 45// * L3 cache included 46class MinimalConfig(n: Int = 1) extends Config( 47 new DefaultConfig(n).alter((site, here, up) => { 48 case SoCParamsKey => up(SoCParamsKey).copy( 49 cores = up(SoCParamsKey).cores.map(_.copy( 50 DecodeWidth = 2, 51 RenameWidth = 2, 52 FetchWidth = 4, 53 IssQueSize = 8, 54 NRPhyRegs = 64, 55 LoadQueueSize = 16, 56 StoreQueueSize = 12, 57 RoqSize = 32, 58 BrqSize = 8, 59 FtqSize = 8, 60 IBufSize = 16, 61 StoreBufferSize = 4, 62 StoreBufferThreshold = 3, 63 dpParams = DispatchParameters( 64 IntDqSize = 12, 65 FpDqSize = 12, 66 LsDqSize = 12, 67 IntDqDeqWidth = 4, 68 FpDqDeqWidth = 4, 69 LsDqDeqWidth = 4 70 ), 71 exuParameters = ExuParameters( 72 JmpCnt = 1, 73 AluCnt = 2, 74 MulCnt = 0, 75 MduCnt = 1, 76 FmacCnt = 1, 77 FmiscCnt = 1, 78 FmiscDivSqrtCnt = 0, 79 LduCnt = 2, 80 StuCnt = 2 81 ), 82 icacheParameters = ICacheParameters( 83 nSets = 64, // 16KB ICache 84 tagECC = Some("parity"), 85 dataECC = Some("parity"), 86 replacer = Some("setplru"), 87 nMissEntries = 2 88 ), 89 dcacheParameters = DCacheParameters( 90 nSets = 64, // 32KB DCache 91 nWays = 8, 92 tagECC = Some("secded"), 93 dataECC = Some("secded"), 94 replacer = Some("setplru"), 95 nMissEntries = 4, 96 nProbeEntries = 4, 97 nReleaseEntries = 4, 98 nStoreReplayEntries = 4, 99 ), 100 EnableBPD = false, // disable TAGE 101 EnableLoop = false, 102 TlbEntrySize = 4, 103 TlbSPEntrySize = 2, 104 PtwL1EntrySize = 2, 105 PtwL2EntrySize = 64, 106 PtwL3EntrySize = 128, 107 PtwSPEntrySize = 2, 108 useFakeL2Cache = true, // disable L2 Cache 109 )), 110 L3Size = 256 * 1024, // 256KB L3 Cache 111 ) 112 }) 113) 114 115// Non-synthesizable MinimalConfig, for fast simulation only 116class MinimalSimConfig(n: Int = 1) extends Config( 117 new MinimalConfig(n).alter((site, here, up) => { 118 case SoCParamsKey => up(SoCParamsKey).copy( 119 cores = up(SoCParamsKey).cores.map(_.copy( 120 useFakeDCache = true, 121 useFakePTW = true, 122 useFakeL1plusCache = true, 123 )), 124 useFakeL3Cache = true 125 ) 126 }) 127) 128 129class MinimalSimConfigForFetch(n: Int = 1) extends Config( 130 new MinimalSimConfig(n).alter((site, here, up) => { 131 case SoCParamsKey => up(SoCParamsKey).copy( 132 cores = up(SoCParamsKey).cores.map(_.copy( 133 FetchWidth = 8, 134 EnableSC = false 135 )) 136 ) 137 }) 138) 139