1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16// See LICENSE.SiFive for license details. 17 18package xiangshan.cache 19 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import xiangshan.{HasXSParameter, XSBundle, XSModule} 24 25// this file contains common building blocks that can be shared by ICache and DCache 26// this is the common parameter base for L1 ICache and L1 DCache 27trait L1CacheParameters { 28 def nSets: Int 29 def nWays: Int 30 def rowBits: Int 31 def blockBytes: Int 32} 33 34trait HasL1CacheParameters extends HasXSParameter 35 with MemoryOpConstants { 36 val cacheParams: L1CacheParameters 37 38 def nSets = cacheParams.nSets 39 def nWays = cacheParams.nWays 40 def blockBytes = cacheParams.blockBytes 41 def blockBits = blockBytes * 8 42 43 def idxBits = log2Up(cacheParams.nSets) 44 def wayBits = log2Up(nWays) 45 def blockOffBits = log2Up(cacheParams.blockBytes) 46 47 def untagBits = blockOffBits + idxBits 48 // 4K page 49 def pgIdxBits = 12 50 def pgUntagBits = untagBits min pgIdxBits 51 def tagBits = PAddrBits - pgUntagBits 52 53 // the basic unit at which we store contents 54 // SRAM bank width 55 def rowBits = cacheParams.rowBits 56 def rowBytes = rowBits/8 57 def rowOffBits = log2Up(rowBytes) 58 // the number of rows in a block 59 def blockRows = blockBytes / rowBytes 60 61 // outer bus width 62 def beatBits = l1BusDataWidth 63 def beatBytes = beatBits / 8 64 def refillCycles = blockBytes / beatBytes 65 def beatOffBits = log2Up(beatBytes) 66 67 // inner bus width(determined by XLEN) 68 def wordBits = DataBits 69 def wordBytes = wordBits / 8 70 def wordOffBits = log2Up(wordBytes) 71 // the number of words in a block 72 def blockWords = blockBytes / wordBytes 73 74 def idxMSB = untagBits-1 75 def idxLSB = blockOffBits 76 def offsetmsb = idxLSB-1 77 def offsetlsb = wordOffBits 78 79 def get_tag(addr: UInt) = (addr >> untagBits).asUInt() 80 def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits) 81 def get_block(addr: UInt) = addr >> blockOffBits 82 def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits 83 84 def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits) 85 def get_row(addr: UInt) = addr(blockOffBits - 1, rowOffBits) 86 def get_word(addr: UInt) = addr(blockOffBits - 1, wordOffBits) 87 88 def beatRows = beatBits/rowBits 89 def rowWords = rowBits/wordBits 90 91 def full_divide(a: Int, b: Int) = a >= b && isPow2(a / b) 92} 93 94abstract class L1CacheModule(implicit p: Parameters) extends XSModule 95 with HasL1CacheParameters 96 97abstract class L1CacheBundle(implicit p: Parameters) extends XSBundle 98 with HasL1CacheParameters 99