1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 32, 90 RasSpecSize: Int = 64, 91 RasCtrSize: Int = 8, 92 CacheLineSize: Int = 512, 93 FtbWays: Int = 4, 94 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 // Seq(( 2048, 2, 8), 97 // ( 2048, 9, 8), 98 // ( 2048, 13, 8), 99 // ( 2048, 20, 8), 100 // ( 2048, 26, 8), 101 // ( 2048, 44, 8), 102 // ( 2048, 73, 8), 103 // ( 2048, 256, 8)), 104 Seq(( 4096, 8, 8), 105 ( 4096, 13, 8), 106 ( 4096, 32, 8), 107 ( 4096, 119, 8)), 108 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 109 // Sets Hist Tag 110 Seq(( 256, 4, 9), 111 ( 256, 8, 9), 112 ( 512, 13, 9), 113 ( 512, 16, 9), 114 ( 512, 32, 9)), 115 SCNRows: Int = 512, 116 SCNTables: Int = 4, 117 SCCtrBits: Int = 6, 118 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 119 numBr: Int = 2, 120 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 121 ((resp_in: BranchPredictionResp, p: Parameters) => { 122 val ftb = Module(new FTB()(p)) 123 val ubtb =Module(new FauFTB()(p)) 124 // val bim = Module(new BIM()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(ubtb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 // ubtb.io.resp_in(0) := resp_in 132 // bim.io.resp_in(0) := ubtb.io.resp 133 // btb.io.resp_in(0) := bim.io.resp 134 // tage.io.resp_in(0) := btb.io.resp 135 // loop.io.resp_in(0) := tage.io.resp 136 ubtb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := ubtb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }), 144 IBufSize: Int = 48, 145 DecodeWidth: Int = 6, 146 RenameWidth: Int = 6, 147 CommitWidth: Int = 6, 148 MaxUopSize: Int = 65, 149 EnableRenameSnapshot: Boolean = true, 150 RenameSnapshotNum: Int = 4, 151 FtqSize: Int = 64, 152 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 153 IntLogicRegs: Int = 32, 154 FpLogicRegs: Int = 33, 155 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 156 VCONFIG_IDX: Int = 32, 157 NRPhyRegs: Int = 192, 158 VirtualLoadQueueSize: Int = 80, 159 LoadQueueRARSize: Int = 80, 160 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 161 RollbackGroupSize: Int = 8, 162 LoadQueueReplaySize: Int = 72, 163 LoadUncacheBufferSize: Int = 20, 164 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 165 StoreQueueSize: Int = 64, 166 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 167 StoreQueueForwardWithMask: Boolean = true, 168 VlsQueueSize: Int = 8, 169 RobSize: Int = 256, 170 RabSize: Int = 256, 171 IssueQueueSize: Int = 32, 172 dpParams: DispatchParameters = DispatchParameters( 173 IntDqSize = 16, 174 FpDqSize = 16, 175 LsDqSize = 16, 176 IntDqDeqWidth = 6, 177 FpDqDeqWidth = 6, 178 LsDqDeqWidth = 6, 179 ), 180 intPreg: PregParams = IntPregParams( 181 numEntries = 192, 182 numRead = None, 183 numWrite = None, 184 ), 185 vfPreg: VfPregParams = VfPregParams( 186 numEntries = 192, 187 numRead = None, 188 numWrite = None, 189 ), 190 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 191 LoadPipelineWidth: Int = 2, 192 StorePipelineWidth: Int = 2, 193 VecMemSrcInWidth: Int = 2, 194 VecMemInstWbWidth: Int = 1, 195 VecMemDispatchWidth: Int = 1, 196 StoreBufferSize: Int = 16, 197 StoreBufferThreshold: Int = 7, 198 EnsbufferWidth: Int = 2, 199 UncacheBufferSize: Int = 4, 200 EnableLoadToLoadForward: Boolean = true, 201 EnableFastForward: Boolean = true, 202 EnableLdVioCheckAfterReset: Boolean = true, 203 EnableSoftPrefetchAfterReset: Boolean = true, 204 EnableCacheErrorAfterReset: Boolean = true, 205 EnableAccurateLoadError: Boolean = true, 206 EnableUncacheWriteOutstanding: Boolean = false, 207 EnableStorePrefetchAtIssue: Boolean = false, 208 EnableStorePrefetchAtCommit: Boolean = false, 209 EnableAtCommitMissTrigger: Boolean = true, 210 EnableStorePrefetchSMS: Boolean = false, 211 EnableStorePrefetchSPB: Boolean = false, 212 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 213 ReSelectLen: Int = 7, // load replay queue replay select counter len 214 iwpuParameters: WPUParameters = WPUParameters( 215 enWPU = false, 216 algoName = "mmru", 217 isICache = true, 218 ), 219 dwpuParameters: WPUParameters = WPUParameters( 220 enWPU = false, 221 algoName = "mmru", 222 enCfPred = false, 223 isICache = false, 224 ), 225 itlbParameters: TLBParameters = TLBParameters( 226 name = "itlb", 227 fetchi = true, 228 useDmode = false, 229 NWays = 48, 230 ), 231 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 232 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 233 ldtlbParameters: TLBParameters = TLBParameters( 234 name = "ldtlb", 235 NWays = 48, 236 outReplace = false, 237 partialStaticPMP = true, 238 outsideRecvFlush = true, 239 saveLevel = true 240 ), 241 sttlbParameters: TLBParameters = TLBParameters( 242 name = "sttlb", 243 NWays = 48, 244 outReplace = false, 245 partialStaticPMP = true, 246 outsideRecvFlush = true, 247 saveLevel = true 248 ), 249 pftlbParameters: TLBParameters = TLBParameters( 250 name = "pftlb", 251 NWays = 48, 252 outReplace = false, 253 partialStaticPMP = true, 254 outsideRecvFlush = true, 255 saveLevel = true 256 ), 257 refillBothTlb: Boolean = false, 258 btlbParameters: TLBParameters = TLBParameters( 259 name = "btlb", 260 NWays = 48, 261 ), 262 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 263 NumPerfCounters: Int = 16, 264 icacheParameters: ICacheParameters = ICacheParameters( 265 tagECC = Some("parity"), 266 dataECC = Some("parity"), 267 replacer = Some("setplru"), 268 nMissEntries = 2, 269 nProbeEntries = 2, 270 nPrefetchEntries = 12, 271 nPrefBufferEntries = 32, 272 ), 273 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 274 tagECC = Some("secded"), 275 dataECC = Some("secded"), 276 replacer = Some("setplru"), 277 nMissEntries = 16, 278 nProbeEntries = 8, 279 nReleaseEntries = 18, 280 nMaxPrefetchEntry = 6, 281 )), 282 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 283 name = "l2", 284 ways = 8, 285 sets = 1024, // default 512KB L2 286 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 287 )), 288 L2NBanks: Int = 1, 289 usePTWRepeater: Boolean = false, 290 softTLB: Boolean = false, // dpi-c l1tlb debug only 291 softPTW: Boolean = false, // dpi-c l2tlb debug only 292 softPTWDelay: Int = 1 293){ 294 def vlWidth = log2Up(VLEN) + 1 295 296 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 297 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 298 299 val intSchdParams = { 300 implicit val schdType: SchedulerType = IntScheduler() 301 SchdBlockParams(Seq( 302 IssueBlockParams(Seq( 303 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 304 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 305 ), numEntries = IssueQueueSize, numEnq = 2), 306 IssueBlockParams(Seq( 307 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 308 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 309 ), numEntries = IssueQueueSize, numEnq = 2), 310 IssueBlockParams(Seq( 311 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 312 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 313 ), numEntries = IssueQueueSize, numEnq = 2), 314 IssueBlockParams(Seq( 315 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))), 316 ), numEntries = IssueQueueSize, numEnq = 2), 317 IssueBlockParams(Seq( 318 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))), 319 ), numEntries = IssueQueueSize, numEnq = 2), 320 ), 321 numPregs = intPreg.numEntries, 322 numDeqOutside = 0, 323 schdType = schdType, 324 rfDataWidth = intPreg.dataCfg.dataWidth, 325 numUopIn = dpParams.IntDqDeqWidth, 326 ) 327 } 328 val vfSchdParams = { 329 implicit val schdType: SchedulerType = VfScheduler() 330 SchdBlockParams(Seq( 331 IssueBlockParams(Seq( 332 ExeUnitParams("FEX0", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(12, 0)), Seq(VfRD(13, 0)))), 333 ), numEntries = IssueQueueSize, numEnq = 2), 334 IssueBlockParams(Seq( 335 ExeUnitParams("VEX0", Seq(VialuCfg, VimacCfg, VppuCfg, VipuCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 336 ), numEntries = IssueQueueSize, numEnq = 2), 337 IssueBlockParams(Seq( 338 ExeUnitParams("VEX1", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 2, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 339 ExeUnitParams("VEX2", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 3, 0), IntWB(port = 9, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 340 ), numEntries = IssueQueueSize, numEnq = 2), 341 IssueBlockParams(Seq( 342 ExeUnitParams("VEX3", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 343 ), numEntries = IssueQueueSize, numEnq = 2), 344 IssueBlockParams(Seq( 345 ExeUnitParams("VEX4", Seq(VfcvtCfg), Seq(VfWB(port = 8, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(10, 1)), Seq(VfRD(11, 1)))), 346 ), numEntries = IssueQueueSize, numEnq = 2), 347 ), 348 numPregs = vfPreg.numEntries, 349 numDeqOutside = 0, 350 schdType = schdType, 351 rfDataWidth = vfPreg.dataCfg.dataWidth, 352 numUopIn = dpParams.FpDqDeqWidth, 353 ) 354 } 355 356 val memSchdParams = { 357 implicit val schdType: SchedulerType = MemScheduler() 358 val rfDataWidth = 64 359 360 SchdBlockParams(Seq( 361 IssueBlockParams(Seq( 362 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))), 363 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))), 364 ), numEntries = IssueQueueSize, numEnq = 2), 365 IssueBlockParams(Seq( 366 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(10, 0)), Seq(Seq(IntRD(12, 0)))), 367 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(11, 0)), Seq(Seq(IntRD(13, 0)))), 368 ), numEntries = IssueQueueSize, numEnq = 2), 369 IssueBlockParams(Seq( 370 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))), 371 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(10, Int.MaxValue)))), 372 ), numEntries = IssueQueueSize, numEnq = 2), 373 IssueBlockParams(Seq( 374 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 375 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 376 ), numEntries = IssueQueueSize, numEnq = 2), 377 ), 378 numPregs = intPreg.numEntries max vfPreg.numEntries, 379 numDeqOutside = 0, 380 schdType = schdType, 381 rfDataWidth = rfDataWidth, 382 numUopIn = dpParams.LsDqDeqWidth, 383 ) 384 } 385 386 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 387 388 def iqWakeUpParams = { 389 Seq( 390 WakeUpConfig( 391 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "LDU0", "LDU1") -> 392 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "LDU0", "LDU1", "STA0", "STA1", "STD0", "STD1") 393 ), 394 WakeUpConfig(Seq("IMISC0") -> Seq("FEX0")), 395 ).flatten 396 } 397 398 def backendParams: BackendParams = backend.BackendParams( 399 Map( 400 IntScheduler() -> intSchdParams, 401 VfScheduler() -> vfSchdParams, 402 MemScheduler() -> memSchdParams, 403 ), 404 Seq( 405 intPreg, 406 vfPreg, 407 ), 408 iqWakeUpParams, 409 ) 410} 411 412case object DebugOptionsKey extends Field[DebugOptions] 413 414case class DebugOptions 415( 416 FPGAPlatform: Boolean = false, 417 EnableDifftest: Boolean = false, 418 AlwaysBasicDiff: Boolean = true, 419 EnableDebug: Boolean = false, 420 EnablePerfDebug: Boolean = true, 421 UseDRAMSim: Boolean = false, 422 EnableConstantin: Boolean = false, 423 EnableChiselDB: Boolean = false, 424 AlwaysBasicDB: Boolean = true, 425 EnableTopDown: Boolean = false, 426 EnableRollingDB: Boolean = false 427) 428 429trait HasXSParameter { 430 431 implicit val p: Parameters 432 433 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 434 435 val coreParams = p(XSCoreParamsKey) 436 val env = p(DebugOptionsKey) 437 438 val XLEN = coreParams.XLEN 439 val VLEN = coreParams.VLEN 440 val ELEN = coreParams.ELEN 441 val minFLen = 32 442 val fLen = 64 443 def xLen = XLEN 444 445 val HasMExtension = coreParams.HasMExtension 446 val HasCExtension = coreParams.HasCExtension 447 val HasDiv = coreParams.HasDiv 448 val HasIcache = coreParams.HasICache 449 val HasDcache = coreParams.HasDCache 450 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 451 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 452 val AsidLength = coreParams.AsidLength 453 val ReSelectLen = coreParams.ReSelectLen 454 val AddrBytes = AddrBits / 8 // unused 455 val DataBits = XLEN 456 val DataBytes = DataBits / 8 457 val VDataBytes = VLEN / 8 458 val HasFPU = coreParams.HasFPU 459 val HasVPU = coreParams.HasVPU 460 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 461 val FetchWidth = coreParams.FetchWidth 462 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 463 val EnableBPU = coreParams.EnableBPU 464 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 465 val EnableRAS = coreParams.EnableRAS 466 val EnableLB = coreParams.EnableLB 467 val EnableLoop = coreParams.EnableLoop 468 val EnableSC = coreParams.EnableSC 469 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 470 val HistoryLength = coreParams.HistoryLength 471 val EnableGHistDiff = coreParams.EnableGHistDiff 472 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 473 val UbtbGHRLength = coreParams.UbtbGHRLength 474 val UbtbSize = coreParams.UbtbSize 475 val EnableFauFTB = coreParams.EnableFauFTB 476 val FtbSize = coreParams.FtbSize 477 val FtbWays = coreParams.FtbWays 478 val RasSize = coreParams.RasSize 479 val RasSpecSize = coreParams.RasSpecSize 480 val RasCtrSize = coreParams.RasCtrSize 481 482 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 483 coreParams.branchPredictor(resp_in, p) 484 } 485 val numBr = coreParams.numBr 486 val TageTableInfos = coreParams.TageTableInfos 487 val TageBanks = coreParams.numBr 488 val SCNRows = coreParams.SCNRows 489 val SCCtrBits = coreParams.SCCtrBits 490 val SCHistLens = coreParams.SCHistLens 491 val SCNTables = coreParams.SCNTables 492 493 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 494 case ((n, cb), h) => (n, cb, h) 495 } 496 val ITTageTableInfos = coreParams.ITTageTableInfos 497 type FoldedHistoryInfo = Tuple2[Int, Int] 498 val foldedGHistInfos = 499 (TageTableInfos.map{ case (nRows, h, t) => 500 if (h > 0) 501 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 502 else 503 Set[FoldedHistoryInfo]() 504 }.reduce(_++_).toSet ++ 505 SCTableInfos.map{ case (nRows, _, h) => 506 if (h > 0) 507 Set((h, min(log2Ceil(nRows/TageBanks), h))) 508 else 509 Set[FoldedHistoryInfo]() 510 }.reduce(_++_).toSet ++ 511 ITTageTableInfos.map{ case (nRows, h, t) => 512 if (h > 0) 513 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 514 else 515 Set[FoldedHistoryInfo]() 516 }.reduce(_++_) ++ 517 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 518 ).toList 519 520 521 522 val CacheLineSize = coreParams.CacheLineSize 523 val CacheLineHalfWord = CacheLineSize / 16 524 val ExtHistoryLength = HistoryLength + 64 525 val IBufSize = coreParams.IBufSize 526 val DecodeWidth = coreParams.DecodeWidth 527 val RenameWidth = coreParams.RenameWidth 528 val CommitWidth = coreParams.CommitWidth 529 val MaxUopSize = coreParams.MaxUopSize 530 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 531 val RenameSnapshotNum = coreParams.RenameSnapshotNum 532 val FtqSize = coreParams.FtqSize 533 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 534 val IntLogicRegs = coreParams.IntLogicRegs 535 val FpLogicRegs = coreParams.FpLogicRegs 536 val VecLogicRegs = coreParams.VecLogicRegs 537 val VCONFIG_IDX = coreParams.VCONFIG_IDX 538 val IntPhyRegs = coreParams.intPreg.numEntries 539 val VfPhyRegs = coreParams.vfPreg.numEntries 540 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 541 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 542 val RobSize = coreParams.RobSize 543 val RabSize = coreParams.RabSize 544 val IntRefCounterWidth = log2Ceil(RobSize) 545 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 546 val LoadQueueRARSize = coreParams.LoadQueueRARSize 547 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 548 val RollbackGroupSize = coreParams.RollbackGroupSize 549 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 550 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 551 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 552 val StoreQueueSize = coreParams.StoreQueueSize 553 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 554 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 555 val VlsQueueSize = coreParams.VlsQueueSize 556 val dpParams = coreParams.dpParams 557 558 def backendParams: BackendParams = coreParams.backendParams 559 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 560 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 561 562 val NumRedirect = backendParams.numRedirect 563 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 564 val LoadPipelineWidth = coreParams.LoadPipelineWidth 565 val StorePipelineWidth = coreParams.StorePipelineWidth 566 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 567 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 568 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 569 val StoreBufferSize = coreParams.StoreBufferSize 570 val StoreBufferThreshold = coreParams.StoreBufferThreshold 571 val EnsbufferWidth = coreParams.EnsbufferWidth 572 val UncacheBufferSize = coreParams.UncacheBufferSize 573 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 574 val EnableFastForward = coreParams.EnableFastForward 575 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 576 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 577 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 578 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 579 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 580 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 581 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 582 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 583 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 584 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 585 val asidLen = coreParams.MMUAsidLen 586 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 587 val refillBothTlb = coreParams.refillBothTlb 588 val iwpuParam = coreParams.iwpuParameters 589 val dwpuParam = coreParams.dwpuParameters 590 val itlbParams = coreParams.itlbParameters 591 val ldtlbParams = coreParams.ldtlbParameters 592 val sttlbParams = coreParams.sttlbParameters 593 val pftlbParams = coreParams.pftlbParameters 594 val btlbParams = coreParams.btlbParameters 595 val l2tlbParams = coreParams.l2tlbParameters 596 val NumPerfCounters = coreParams.NumPerfCounters 597 598 val instBytes = if (HasCExtension) 2 else 4 599 val instOffsetBits = log2Ceil(instBytes) 600 601 val icacheParameters = coreParams.icacheParameters 602 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 603 604 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 605 // for constrained LR/SC loop 606 val LRSCCycles = 64 607 // for lr storm 608 val LRSCBackOff = 8 609 610 // cache hierarchy configurations 611 val l1BusDataWidth = 256 612 613 // load violation predict 614 val ResetTimeMax2Pow = 20 //1078576 615 val ResetTimeMin2Pow = 10 //1024 616 // wait table parameters 617 val WaitTableSize = 1024 618 val MemPredPCWidth = log2Up(WaitTableSize) 619 val LWTUse2BitCounter = true 620 // store set parameters 621 val SSITSize = WaitTableSize 622 val LFSTSize = 32 623 val SSIDWidth = log2Up(LFSTSize) 624 val LFSTWidth = 4 625 val StoreSetEnable = true // LWT will be disabled if SS is enabled 626 val LFSTEnable = false 627 628 val PCntIncrStep: Int = 6 629 val numPCntHc: Int = 25 630 val numPCntPtw: Int = 19 631 632 val numCSRPCntFrontend = 8 633 val numCSRPCntCtrl = 8 634 val numCSRPCntLsu = 8 635 val numCSRPCntHc = 5 636} 637