1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.regfile 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23 24class RfReadPort(len: Int)(implicit p: Parameters) extends XSBundle { 25 val addr = Input(UInt(PhyRegIdxWidth.W)) 26 val data = Output(UInt(len.W)) 27 override def cloneType: RfReadPort.this.type = 28 new RfReadPort(len).asInstanceOf[this.type] 29} 30 31class RfWritePort(len: Int)(implicit p: Parameters) extends XSBundle { 32 val wen = Input(Bool()) 33 val addr = Input(UInt(PhyRegIdxWidth.W)) 34 val data = Input(UInt(len.W)) 35 override def cloneType: RfWritePort.this.type = 36 new RfWritePort(len).asInstanceOf[this.type] 37} 38 39class Regfile 40( 41 numReadPorts: Int, 42 numWirtePorts: Int, 43 hasZero: Boolean, 44 len: Int 45)(implicit p: Parameters) extends XSModule { 46 val io = IO(new Bundle() { 47 val readPorts = Vec(numReadPorts, new RfReadPort(len)) 48 val writePorts = Vec(numWirtePorts, new RfWritePort(len)) 49 val debug_rports = Vec(32, new RfReadPort(len)) 50 }) 51 52 println("Regfile: size:" + NRPhyRegs + " read: " + numReadPorts + " write: " + numWirtePorts) 53 54 val useBlackBox = false 55 if (!useBlackBox) { 56 val mem = Reg(Vec(NRPhyRegs, UInt(len.W))) 57 for (r <- io.readPorts) { 58 val rdata = if (hasZero) Mux(r.addr === 0.U, 0.U, mem(r.addr)) else mem(r.addr) 59 r.data := RegNext(rdata) 60 } 61 for (w <- io.writePorts) { 62 when(w.wen) { 63 mem(w.addr) := w.data 64 } 65 } 66 67 for (rport <- io.debug_rports) { 68 val zero_rdata = Mux(rport.addr === 0.U, 0.U, mem(rport.addr)) 69 rport.data := (if (hasZero) zero_rdata else mem(rport.addr)) 70 } 71 when (reset.asBool()) { 72 mem.map(_ := 0.U) 73 } 74 } else { 75 76 val regfile = Module(new regfile_160x64_10w16r_sim) 77 78 regfile.io.clk := this.clock 79 regfile.io.gpr := hasZero.B 80 81 regfile.io.wen0 := io.writePorts(0).wen 82 regfile.io.waddr0 := io.writePorts(0).addr 83 regfile.io.wdata0 := io.writePorts(0).data 84 85 regfile.io.wen1 := io.writePorts(1).wen 86 regfile.io.waddr1 := io.writePorts(1).addr 87 regfile.io.wdata1 := io.writePorts(1).data 88 89 regfile.io.wen2 := io.writePorts(2).wen 90 regfile.io.waddr2 := io.writePorts(2).addr 91 regfile.io.wdata2 := io.writePorts(2).data 92 93 regfile.io.wen3 := io.writePorts(3).wen 94 regfile.io.waddr3 := io.writePorts(3).addr 95 regfile.io.wdata3 := io.writePorts(3).data 96 97 regfile.io.wen4 := io.writePorts(4).wen 98 regfile.io.waddr4 := io.writePorts(4).addr 99 regfile.io.wdata4 := io.writePorts(4).data 100 101 regfile.io.wen5 := io.writePorts(5).wen 102 regfile.io.waddr5 := io.writePorts(5).addr 103 regfile.io.wdata5 := io.writePorts(5).data 104 105 regfile.io.wen6 := io.writePorts(6).wen 106 regfile.io.waddr6 := io.writePorts(6).addr 107 regfile.io.wdata6 := io.writePorts(6).data 108 109 regfile.io.wen7 := io.writePorts(7).wen 110 regfile.io.waddr7 := io.writePorts(7).addr 111 regfile.io.wdata7 := io.writePorts(7).data 112 113 regfile.io.wen8 := false.B //io.writePorts(8).wen 114 regfile.io.waddr8 := DontCare //io.writePorts(8).addr 115 regfile.io.wdata8 := DontCare //io.writePorts(8).data 116 117 regfile.io.wen9 := false.B //io.writePorts(9).wen 118 regfile.io.waddr9 := DontCare //io.writePorts(9).addr 119 regfile.io.wdata9 := DontCare //io.writePorts(9).data 120 121 122 regfile.io.raddr0 := io.readPorts(0).addr 123 regfile.io.raddr1 := io.readPorts(1).addr 124 regfile.io.raddr2 := io.readPorts(2).addr 125 regfile.io.raddr3 := io.readPorts(3).addr 126 regfile.io.raddr4 := io.readPorts(4).addr 127 regfile.io.raddr5 := io.readPorts(5).addr 128 regfile.io.raddr6 := io.readPorts(6).addr 129 regfile.io.raddr7 := io.readPorts(7).addr 130 regfile.io.raddr8 := io.readPorts(8).addr 131 regfile.io.raddr9 := io.readPorts(9).addr 132 regfile.io.raddr10 := io.readPorts(10).addr 133 regfile.io.raddr11 := io.readPorts(11).addr 134 regfile.io.raddr12 := io.readPorts(12).addr 135 regfile.io.raddr13 := io.readPorts(13).addr 136 regfile.io.raddr14 := DontCare //io.readPorts(14).addr 137 regfile.io.raddr15 := DontCare //io.readPorts(15).addr 138 139 io.readPorts(0).data := regfile.io.rdata0 140 io.readPorts(1).data := regfile.io.rdata1 141 io.readPorts(2).data := regfile.io.rdata2 142 io.readPorts(3).data := regfile.io.rdata3 143 io.readPorts(4).data := regfile.io.rdata4 144 io.readPorts(5).data := regfile.io.rdata5 145 io.readPorts(6).data := regfile.io.rdata6 146 io.readPorts(7).data := regfile.io.rdata7 147 io.readPorts(8).data := regfile.io.rdata8 148 io.readPorts(9).data := regfile.io.rdata9 149 io.readPorts(10).data := regfile.io.rdata10 150 io.readPorts(11).data := regfile.io.rdata11 151 io.readPorts(12).data := regfile.io.rdata12 152 io.readPorts(13).data := regfile.io.rdata13 153 154 io.debug_rports := DontCare 155 } 156 157} 158 159class regfile_160x64_10w16r_sim extends BlackBox with HasBlackBoxResource { 160 161 val io = IO(new Bundle{ 162 val clk = Input(Clock()) 163 val gpr = Input(Bool()) 164 165 // write 166 val wen0, wen1, wen2, wen3, wen4, wen5, wen6, wen7, wen8, wen9 = Input(Bool()) 167 val waddr0, waddr1, waddr2, waddr3, waddr4, waddr5, waddr6, waddr7, waddr8, waddr9 = Input(UInt(8.W)) 168 val wdata0, wdata1, wdata2, wdata3, wdata4, wdata5, wdata6, wdata7, wdata8, wdata9 = Input(UInt(64.W)) 169 170 // read 171 val raddr0, raddr1, raddr2, raddr3, raddr4, raddr5, raddr6, raddr7 = Input(UInt(8.W)) 172 val raddr8, raddr9, raddr10, raddr11, raddr12, raddr13, raddr14, raddr15 = Input(UInt(8.W)) 173 val rdata0, rdata1, rdata2, rdata3, rdata4, rdata5, rdata6, rdata7 = Output(UInt(64.W)) 174 val rdata8, rdata9, rdata10, rdata11, rdata12, rdata13, rdata14, rdata15 = Output(UInt(64.W)) 175 }) 176 177 val vsrc = "/vsrc/regfile_160x64_10w16r_sim.v" 178 println(s"Regfile: Using verilog source at: $vsrc") 179 setResource(vsrc) 180 181} 182 183