xref: /XiangShan/src/main/scala/device/AXI4Timer.scala (revision f320e0f01bd645f0a3045a8a740e60dd770734a9) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chisel3._
20import chipsalliance.rocketchip.config.Parameters
21import freechips.rocketchip.diplomacy.AddressSet
22import utils._
23
24class TimerIO extends Bundle {
25  val mtip = Output(Bool())
26}
27
28class AXI4Timer
29(
30  sim: Boolean = false,
31  address: Seq[AddressSet]
32)(implicit p: Parameters)
33  extends AXI4SlaveModule(address, executable = false, _extra = new TimerIO)
34{
35  override lazy val module = new AXI4SlaveModuleImp[TimerIO](this){
36    val mtime = RegInit(0.U(64.W))  // unit: us
37    val mtimecmp = RegInit(0.U(64.W))
38
39    val clk = (if (!sim) 40 /* 40MHz / 1000000 */ else 10000)
40    val freq = RegInit(clk.U(16.W))
41    val inc = RegInit(1000.U(16.W))
42
43    val cnt = RegInit(0.U(16.W))
44    val nextCnt = cnt + 1.U
45    cnt := Mux(nextCnt < freq, nextCnt, 0.U)
46    val tick = (nextCnt === freq)
47    when (tick) { mtime := mtime + inc }
48
49    val mapping = Map(
50      RegMap(0x4000, mtimecmp),
51      RegMap(0x8000, freq),
52      RegMap(0x8008, inc),
53      RegMap(0xbff8, mtime)
54    )
55    def getOffset(addr: UInt) = addr(15,0)
56
57    RegMap.generate(mapping, getOffset(raddr), in.r.bits.data,
58      getOffset(waddr), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb))
59
60    io.extra.get.mtip := RegNext(mtime >= mtimecmp)
61  }
62}
63