1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache.{DCacheWordIO, MemoryOpConstants} 25import xiangshan.cache.mmu.{TlbRequestIO, TlbCmd} 26import difftest._ 27 28class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{ 29 val io = IO(new Bundle() { 30 val in = Flipped(Decoupled(new ExuInput)) 31 val storeDataIn = Flipped(Valid(new StoreDataBundle)) // src2 from rs 32 val out = Decoupled(new ExuOutput) 33 val dcache = new DCacheWordIO 34 val dtlb = new TlbRequestIO 35 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 36 val flush_sbuffer = new SbufferFlushBundle 37 val rsFeedback = ValidIO(new RSFeedback) 38 val redirect = Flipped(ValidIO(new Redirect)) 39 val flush = Input(Bool()) 40 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 41 }) 42 43 //------------------------------------------------------- 44 // Atomics Memory Accsess FSM 45 //------------------------------------------------------- 46 val s_invalid :: s_tlb :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7) 47 val state = RegInit(s_invalid) 48 val addr_valid = RegInit(false.B) 49 val data_valid = RegInit(false.B) 50 val in = Reg(new ExuInput()) 51 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 52 val atom_override_xtval = RegInit(false.B) 53 // paddr after translation 54 val paddr = Reg(UInt()) 55 val is_mmio = Reg(Bool()) 56 // dcache response data 57 val resp_data = Reg(UInt()) 58 val resp_data_wire = WireInit(0.U) 59 val is_lrsc_valid = Reg(Bool()) 60 61 // Difftest signals 62 val paddr_reg = Reg(UInt(64.W)) 63 val data_reg = Reg(UInt(64.W)) 64 val mask_reg = Reg(UInt(8.W)) 65 val fuop_reg = Reg(UInt(8.W)) 66 67 io.exceptionAddr.valid := atom_override_xtval 68 io.exceptionAddr.bits := in.src(0) 69 70 // assign default value to output signals 71 io.in.ready := false.B 72 io.out.valid := false.B 73 io.out.bits := DontCare 74 75 io.dcache.req.valid := false.B 76 io.dcache.req.bits := DontCare 77 io.dcache.resp.ready := false.B 78 79 io.dtlb.req.valid := false.B 80 io.dtlb.req.bits := DontCare 81 io.dtlb.resp.ready := false.B 82 83 io.flush_sbuffer.valid := false.B 84 85 XSDebug("state: %d\n", state) 86 87 when (state === s_invalid) { 88 io.in.ready := true.B 89 when (io.in.fire()) { 90 in := io.in.bits 91 in.src(1) := in.src(1) // leave src2 unchanged 92 addr_valid := true.B 93 } 94 when (io.storeDataIn.fire()) { 95 in.src(1) := io.storeDataIn.bits.data 96 data_valid := true.B 97 } 98 when(data_valid && addr_valid) { 99 state := s_tlb 100 addr_valid := false.B 101 data_valid := false.B 102 } 103 } 104 105 106 // Send TLB feedback to store issue queue 107 // we send feedback right after we receives request 108 // also, we always treat amo as tlb hit 109 // since we will continue polling tlb all by ourself 110 io.rsFeedback.valid := RegNext(RegNext(io.in.valid)) 111 io.rsFeedback.bits.hit := true.B 112 io.rsFeedback.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 113 io.rsFeedback.bits.flushState := DontCare 114 io.rsFeedback.bits.sourceType := DontCare 115 116 // tlb translation, manipulating signals && deal with exception 117 when (state === s_tlb) { 118 // send req to dtlb 119 // keep firing until tlb hit 120 io.dtlb.req.valid := true.B 121 io.dtlb.req.bits.vaddr := in.src(0) 122 io.dtlb.req.bits.roqIdx := in.uop.roqIdx 123 io.dtlb.resp.ready := true.B 124 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 125 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 126 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 127 io.dtlb.req.bits.debug.isFirstIssue := false.B 128 129 when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){ 130 // exception handling 131 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 132 "b00".U -> true.B, //b 133 "b01".U -> (in.src(0)(0) === 0.U), //h 134 "b10".U -> (in.src(0)(1,0) === 0.U), //w 135 "b11".U -> (in.src(0)(2,0) === 0.U) //d 136 )) 137 exceptionVec(storeAddrMisaligned) := !addrAligned 138 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 139 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 140 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 141 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 142 val exception = !addrAligned || 143 io.dtlb.resp.bits.excp.pf.st || 144 io.dtlb.resp.bits.excp.pf.ld || 145 io.dtlb.resp.bits.excp.af.st || 146 io.dtlb.resp.bits.excp.af.ld 147 is_mmio := io.dtlb.resp.bits.mmio 148 when (exception) { 149 // check for exceptions 150 // if there are exceptions, no need to execute it 151 state := s_finish 152 atom_override_xtval := true.B 153 } .otherwise { 154 paddr := io.dtlb.resp.bits.paddr 155 state := s_flush_sbuffer_req 156 } 157 } 158 } 159 160 161 when (state === s_flush_sbuffer_req) { 162 io.flush_sbuffer.valid := true.B 163 state := s_flush_sbuffer_resp 164 } 165 166 when (state === s_flush_sbuffer_resp) { 167 when (io.flush_sbuffer.empty) { 168 state := s_cache_req 169 } 170 } 171 172 when (state === s_cache_req) { 173 io.dcache.req.valid := true.B 174 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 175 LSUOpType.lr_w -> M_XLR, 176 LSUOpType.sc_w -> M_XSC, 177 LSUOpType.amoswap_w -> M_XA_SWAP, 178 LSUOpType.amoadd_w -> M_XA_ADD, 179 LSUOpType.amoxor_w -> M_XA_XOR, 180 LSUOpType.amoand_w -> M_XA_AND, 181 LSUOpType.amoor_w -> M_XA_OR, 182 LSUOpType.amomin_w -> M_XA_MIN, 183 LSUOpType.amomax_w -> M_XA_MAX, 184 LSUOpType.amominu_w -> M_XA_MINU, 185 LSUOpType.amomaxu_w -> M_XA_MAXU, 186 187 LSUOpType.lr_d -> M_XLR, 188 LSUOpType.sc_d -> M_XSC, 189 LSUOpType.amoswap_d -> M_XA_SWAP, 190 LSUOpType.amoadd_d -> M_XA_ADD, 191 LSUOpType.amoxor_d -> M_XA_XOR, 192 LSUOpType.amoand_d -> M_XA_AND, 193 LSUOpType.amoor_d -> M_XA_OR, 194 LSUOpType.amomin_d -> M_XA_MIN, 195 LSUOpType.amomax_d -> M_XA_MAX, 196 LSUOpType.amominu_d -> M_XA_MINU, 197 LSUOpType.amomaxu_d -> M_XA_MAXU 198 )) 199 200 io.dcache.req.bits.addr := paddr 201 io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 202 // TODO: atomics do need mask: fix mask 203 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 204 io.dcache.req.bits.id := DontCare 205 206 when(io.dcache.req.fire()){ 207 state := s_cache_resp 208 paddr_reg := io.dcache.req.bits.addr 209 data_reg := io.dcache.req.bits.data 210 mask_reg := io.dcache.req.bits.mask 211 fuop_reg := in.uop.ctrl.fuOpType 212 } 213 } 214 215 when (state === s_cache_resp) { 216 io.dcache.resp.ready := true.B 217 when(io.dcache.resp.fire()) { 218 is_lrsc_valid := io.dcache.resp.bits.id 219 val rdata = io.dcache.resp.bits.data 220 val rdataSel = LookupTree(paddr(2, 0), List( 221 "b000".U -> rdata(63, 0), 222 "b001".U -> rdata(63, 8), 223 "b010".U -> rdata(63, 16), 224 "b011".U -> rdata(63, 24), 225 "b100".U -> rdata(63, 32), 226 "b101".U -> rdata(63, 40), 227 "b110".U -> rdata(63, 48), 228 "b111".U -> rdata(63, 56) 229 )) 230 231 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 232 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 233 LSUOpType.sc_w -> rdata, 234 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 235 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 236 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 237 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 238 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 239 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 240 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 241 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 242 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 243 244 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 245 LSUOpType.sc_d -> rdata, 246 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 247 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 248 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 249 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 250 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 251 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 252 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 253 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 254 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 255 )) 256 257 resp_data := resp_data_wire 258 state := s_finish 259 } 260 } 261 262 when (state === s_finish) { 263 io.out.valid := true.B 264 io.out.bits.uop := in.uop 265 io.out.bits.uop.cf.exceptionVec := exceptionVec 266 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 267 io.out.bits.data := resp_data 268 io.out.bits.redirectValid := false.B 269 io.out.bits.redirect := DontCare 270 io.out.bits.debug.isMMIO := is_mmio 271 io.out.bits.debug.paddr := paddr 272 when (io.out.fire()) { 273 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 274 state := s_invalid 275 } 276 } 277 278 when(io.redirect.valid || io.flush){ 279 atom_override_xtval := false.B 280 } 281 282 if (!env.FPGAPlatform) { 283 val difftest = Module(new DifftestAtomicEvent) 284 difftest.io.clock := clock 285 difftest.io.coreid := hardId.U 286 difftest.io.atomicResp := io.dcache.resp.fire() 287 difftest.io.atomicAddr := paddr_reg 288 difftest.io.atomicData := data_reg 289 difftest.io.atomicMask := mask_reg 290 difftest.io.atomicFuop := fuop_reg 291 difftest.io.atomicOut := resp_data_wire 292 } 293} 294