1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.fu.FuType._ 30import xiangshan.backend.ctrlblock.DebugLsInfoBundle 31import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 32import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 33 34class StoreUnit(implicit p: Parameters) extends XSModule with HasDCacheParameters { 35 val io = IO(new Bundle() { 36 val redirect = Flipped(ValidIO(new Redirect)) 37 val stin = Flipped(Decoupled(new MemExuInput)) 38 val issue = Valid(new MemExuInput) 39 val tlb = new TlbRequestIO() 40 val dcache = new DCacheStoreIO 41 val pmp = Flipped(new PMPRespBundle()) 42 val lsq = ValidIO(new LsPipelineBundle) 43 val lsq_replenish = Output(new LsPipelineBundle()) 44 val feedback_slow = ValidIO(new RSFeedback) 45 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 46 // provide prefetch info to sms 47 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 48 val stld_nuke_query = Valid(new StoreNukeQueryIO) 49 val stout = DecoupledIO(new MemExuOutput) // writeback store 50 // store mask, send to sq in store_s0 51 val st_mask_out = Valid(new StoreMaskBundle) 52 val debug_ls = Output(new DebugLsInfoBundle) 53 // vector 54 val vecstin = Flipped(Decoupled(new VecStorePipeBundle())) 55 val vec_isFirstIssue = Input(Bool()) 56 val lsq_vec = ValidIO(new LsPipelineBundle) // nuke check between vector stores and scalar loads 57 val vec_feedback_slow = ValidIO(new VSFQFeedback) 58 }) 59 60 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 61 62 // Pipeline 63 // -------------------------------------------------------------------------------- 64 // stage 0 65 // -------------------------------------------------------------------------------- 66 // generate addr, use addr to query DCache and DTLB 67 val s0_iss_valid = io.stin.valid 68 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 69 val s0_vec_valid = io.vecstin.valid 70 val s0_valid = s0_iss_valid || s0_prf_valid || s0_vec_valid 71 val s0_use_flow_vec = s0_vec_valid 72 val s0_use_flow_rs = s0_iss_valid && !s0_vec_valid 73 val s0_use_flow_prf = !s0_iss_valid && !s0_vec_valid && s0_prf_valid 74 val s0_stin = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 75 val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) 76 val s0_uop = Mux(s0_use_flow_rs, s0_stin.uop, s0_vecstin.uop) 77 val s0_isFirstIssue = s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue 78 val s0_rsIdx = Mux(s0_use_flow_rs, io.stin.bits.iqIdx, 0.U) 79 val s0_size = Mux( 80 s0_use_flow_rs, 81 LSUOpType.size(s0_uop.fuOpType), 82 Mux( 83 s0_use_flow_vec, 84 io.vecstin.bits.alignedType, 85 3.U 86 ) 87 ) 88 val s0_mem_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.sqIdx.value, 0.U) 89 val s0_rob_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) 90 val s0_pc = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.pc, 0.U) 91 val s0_instr_type = Mux(s0_use_flow_rs || s0_use_flow_vec, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 92 val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B) 93 val s0_out = Wire(new LsPipelineBundle) 94 val s0_kill = s0_uop.robIdx.needFlush(io.redirect) 95 val s0_can_go = s1_ready 96 val s0_fire = s0_valid && !s0_kill && s0_can_go 97 // vector 98 val s0_exp = !s0_use_flow_vec || s0_vecstin.exp 99 val s0_flowPtr = s0_vecstin.flowPtr 100 val s0_isLastElem = s0_vecstin.isLastElem 101 102 // generate addr 103 // val saddr = s0_in.bits.src(0) + SignExt(s0_in.bits.uop.imm(11,0), VAddrBits) 104 val imm12 = WireInit(s0_uop.imm(11,0)) 105 val saddr_lo = s0_stin.src(0)(11,0) + Cat(0.U(1.W), imm12) 106 val saddr_hi = Mux(saddr_lo(12), 107 Mux(imm12(11), s0_stin.src(0)(VAddrBits-1, 12), s0_stin.src(0)(VAddrBits-1, 12)+1.U), 108 Mux(imm12(11), s0_stin.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), s0_stin.src(0)(VAddrBits-1, 12)), 109 ) 110 val s0_saddr = Cat(saddr_hi, saddr_lo(11,0)) 111 val s0_vaddr = Mux( 112 s0_use_flow_rs, 113 s0_saddr, 114 Mux( 115 s0_use_flow_vec, 116 s0_vecstin.vaddr, 117 io.prefetch_req.bits.vaddr 118 ) 119 ) 120 val s0_mask = Mux( 121 s0_use_flow_rs, 122 genVWmask(s0_saddr, s0_uop.fuOpType(1,0)), 123 Mux( 124 s0_use_flow_vec, 125 s0_vecstin.mask, 126 // -1.asSInt.asUInt 127 Fill(VLEN/8, 1.U(1.W)) 128 ) 129 ) 130 131 io.tlb.req.valid := s0_valid 132 io.tlb.req.bits.vaddr := s0_vaddr 133 io.tlb.req.bits.cmd := TlbCmd.write 134 io.tlb.req.bits.size := s0_size 135 io.tlb.req.bits.kill := false.B 136 io.tlb.req.bits.memidx.is_ld := false.B 137 io.tlb.req.bits.memidx.is_st := true.B 138 io.tlb.req.bits.memidx.idx := s0_mem_idx 139 io.tlb.req.bits.debug.robIdx := s0_rob_idx 140 io.tlb.req.bits.no_translate := false.B 141 io.tlb.req.bits.debug.pc := s0_pc 142 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 143 io.tlb.req_kill := false.B 144 145 // Dcache access here: not **real** dcache write 146 // just read meta and tag in dcache, to find out the store will hit or miss 147 148 // NOTE: The store request does not wait for the dcache to be ready. 149 // If the dcache is not ready at this time, the dcache is not queried. 150 // But, store prefetch request will always wait for dcache to be ready to make progress. 151 io.dcache.req.valid := s0_fire 152 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 153 io.dcache.req.bits.vaddr := s0_vaddr 154 io.dcache.req.bits.instrtype := s0_instr_type 155 156 s0_out := DontCare 157 s0_out.vaddr := s0_vaddr 158 // Now data use its own io 159 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.fuOpType(1,0)) 160 s0_out.data := Mux(s0_use_flow_rs, s0_stin.src(1), s0_vecstin.src_vs3) // FIXME: remove data from pipeline 161 s0_out.uop := s0_uop 162 s0_out.miss := false.B 163 s0_out.rsIdx := s0_rsIdx 164 s0_out.mask := s0_mask 165 s0_out.isFirstIssue := s0_isFirstIssue 166 s0_out.isHWPrefetch := s0_use_flow_prf 167 s0_out.wlineflag := s0_wlineflag 168 s0_out.isvec := s0_use_flow_vec 169 s0_out.is128bit := false.B 170 s0_out.exp := s0_exp 171 s0_out.sflowPtr := s0_flowPtr 172 s0_out.isLastElem := s0_isLastElem 173 when(s0_valid && s0_isFirstIssue) { 174 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 175 } 176 177 // exception check 178 val s0_addr_aligned = LookupTree(Mux(s0_use_flow_vec, s0_vecstin.alignedType, s0_uop.fuOpType(1, 0)), List( 179 "b00".U -> true.B, //b 180 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 181 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 182 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 183 )) 184 s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_flow_rs || s0_use_flow_vec, !s0_addr_aligned, false.B) 185 186 io.st_mask_out.valid := s0_use_flow_rs 187 io.st_mask_out.bits.mask := s0_out.mask 188 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 189 190 io.stin.ready := s1_ready && s0_use_flow_rs 191 io.vecstin.ready := s1_ready && s0_use_flow_vec 192 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid && !s0_vec_valid 193 194 // Pipeline 195 // -------------------------------------------------------------------------------- 196 // stage 1 197 // -------------------------------------------------------------------------------- 198 // TLB resp (send paddr to dcache) 199 val s1_valid = RegInit(false.B) 200 val s1_in = RegEnable(s0_out, s0_fire) 201 val s1_out = Wire(new LsPipelineBundle) 202 val s1_kill = Wire(Bool()) 203 val s1_can_go = s2_ready 204 val s1_fire = s1_valid && !s1_kill && s1_can_go 205 val s1_exp = RegEnable(s0_out.exp, true.B, s0_fire) 206 207 // mmio cbo decoder 208 val s1_mmio_cbo = s1_in.uop.fuOpType === LSUOpType.cbo_clean || 209 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 210 s1_in.uop.fuOpType === LSUOpType.cbo_inval 211 val s1_paddr = io.tlb.resp.bits.paddr(0) 212 val s1_tlb_miss = io.tlb.resp.bits.miss 213 val s1_mmio = s1_mmio_cbo 214 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 215 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 216 val s1_isLastElem = RegEnable(s0_isLastElem, false.B, s0_fire) 217 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || s1_tlb_miss 218 219 s1_ready := !s1_valid || s1_kill || s2_ready 220 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 221 when (s0_fire) { s1_valid := true.B } 222 .elsewhen (s1_fire) { s1_valid := false.B } 223 .elsewhen (s1_kill) { s1_valid := false.B } 224 225 // st-ld violation dectect request. 226 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 227 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 228 io.stld_nuke_query.bits.paddr := s1_paddr 229 io.stld_nuke_query.bits.mask := s1_in.mask 230 231 // issue 232 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isvec 233 io.issue.bits := RegEnable(s0_stin, s0_valid) 234 235 236 // Send TLB feedback to store issue queue 237 // Store feedback is generated in store_s1, sent to RS in store_s2 238 val s1_feedback = Wire(Valid(new RSFeedback)) 239 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch && !s1_isvec 240 s1_feedback.bits.hit := !s1_tlb_miss 241 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 242 s1_feedback.bits.robIdx := s1_out.uop.robIdx 243 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 244 s1_feedback.bits.dataInvalidSqIdx := DontCare 245 246 XSDebug(s1_feedback.valid, 247 "S1 Store: tlbHit: %d robIdx: %d\n", 248 s1_feedback.bits.hit, 249 s1_feedback.bits.robIdx.value 250 ) 251 252 val s1_vec_feedback = Wire(Valid(new VSFQFeedback)) 253 s1_vec_feedback.valid := s1_valid && !s1_in.isHWPrefetch && s1_isvec 254 s1_vec_feedback.bits.flowPtr := s1_out.sflowPtr 255 s1_vec_feedback.bits.hit := !s1_tlb_miss 256 s1_vec_feedback.bits.sourceType := RSFeedbackType.tlbMiss 257 s1_vec_feedback.bits.paddr := s1_paddr 258 s1_vec_feedback.bits.mmio := s1_mmio 259 s1_vec_feedback.bits.atomic := s1_mmio 260 XSDebug(s1_vec_feedback.valid, 261 "Vector S1 Store: tlbHit: %d flowPtr: %d\n", 262 s1_vec_feedback.bits.hit, 263 s1_vec_feedback.bits.flowPtr.value 264 ) 265 266 // io.feedback_slow := s1_feedback 267 // io.vec_feedback_slow := s1_vec_feedback 268 269 // get paddr from dtlb, check if rollback is needed 270 // writeback store inst to lsq 271 s1_out := s1_in 272 s1_out.paddr := s1_paddr 273 s1_out.miss := false.B 274 s1_out.mmio := s1_mmio 275 s1_out.tlbMiss := s1_tlb_miss 276 s1_out.atomic := s1_mmio 277 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st && s1_exp 278 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st && s1_exp 279 280 // scalar store and scalar load nuke check, and also other purposes 281 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch && !s1_isvec 282 io.lsq.bits := s1_out 283 io.lsq.bits.miss := s1_tlb_miss 284 // vector store and scalar load nuke check 285 io.lsq_vec.valid := s1_valid && !s1_in.isHWPrefetch && s1_isvec 286 io.lsq_vec.bits := s1_out 287 io.lsq_vec.bits.miss := s1_tlb_miss 288 io.lsq_vec.bits.isLastElem := s1_isLastElem 289 290 // kill dcache write intent request when tlb miss or exception 291 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 292 io.dcache.s1_paddr := s1_paddr 293 294 // write below io.out.bits assign sentence to prevent overwriting values 295 val s1_tlb_memidx = io.tlb.resp.bits.memidx 296 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 297 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 298 s1_out.uop.debugInfo.tlbRespTime := GTimer() 299 } 300 301 // Pipeline 302 // -------------------------------------------------------------------------------- 303 // stage 2 304 // -------------------------------------------------------------------------------- 305 // mmio check 306 val s2_valid = RegInit(false.B) 307 val s2_in = RegEnable(s1_out, s1_fire) 308 val s2_out = Wire(new LsPipelineBundle) 309 val s2_kill = Wire(Bool()) 310 val s2_can_go = s3_ready 311 val s2_fire = s2_valid && !s2_kill && s2_can_go 312 val s2_exp = RegEnable(s1_out.exp, true.B, s1_fire) 313 314 s2_ready := !s2_valid || s2_kill || s3_ready 315 when (s1_fire) { s2_valid := true.B } 316 .elsewhen (s2_fire) { s2_valid := false.B } 317 .elsewhen (s2_kill) { s2_valid := false.B } 318 319 val s2_pmp = WireInit(io.pmp) 320 321 val s2_exception = ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR 322 val s2_mmio = s2_in.mmio || s2_pmp.mmio 323 s2_kill := (s2_mmio && !s2_exception) || s2_in.uop.robIdx.needFlush(io.redirect) 324 325 s2_out := s2_in 326 s2_out.mmio := s2_mmio && !s2_exception 327 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 328 s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st) && s2_exp 329 330 // kill dcache write intent request when mmio or exception 331 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 332 io.dcache.s2_pc := s2_out.uop.pc 333 // TODO: dcache resp 334 io.dcache.resp.ready := true.B 335 336 // feedback tlb miss to RS in store_s2 337 io.feedback_slow.valid := RegNext(s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) 338 io.feedback_slow.bits := RegNext(s1_feedback.bits) 339 340 // vector feedback 341 io.vec_feedback_slow.valid := RegNext(s1_vec_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) 342 io.vec_feedback_slow.bits := RegNext(s1_vec_feedback.bits) 343 io.vec_feedback_slow.bits.mmio := s2_mmio && !s2_exception 344 io.vec_feedback_slow.bits.atomic := s2_in.atomic || s2_pmp.atomic 345 346 // mmio and exception 347 io.lsq_replenish := s2_out 348 349 // prefetch related 350 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 351 352 // RegNext prefetch train for better timing 353 // ** Now, prefetch train is valid at store s3 ** 354 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true) 355 // override miss bit 356 io.prefetch_train.bits.miss := RegNext(io.dcache.resp.bits.miss) 357 // TODO: add prefetch and access bit 358 io.prefetch_train.bits.meta_prefetch := false.B 359 io.prefetch_train.bits.meta_access := false.B 360 if(EnableStorePrefetchSMS) { 361 io.prefetch_train.valid := RegNext(s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch) 362 }else { 363 io.prefetch_train.valid := false.B 364 } 365 366 // Pipeline 367 // -------------------------------------------------------------------------------- 368 // stage 3 369 // -------------------------------------------------------------------------------- 370 // store write back 371 val s3_valid = RegInit(false.B) 372 val s3_in = RegEnable(s2_out, s2_fire) 373 val s3_out = Wire(new MemExuOutput) 374 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 375 val s3_can_go = s3_ready 376 val s3_fire = s3_valid && !s3_kill && s3_can_go 377 378 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch } 379 .elsewhen (s3_fire) { s3_valid := false.B } 380 .elsewhen (s3_kill) { s3_valid := false.B } 381 382 // wb: writeback 383 val SelectGroupSize = RollbackGroupSize 384 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 385 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 386 387 s3_out := DontCare 388 s3_out.uop := s3_in.uop 389 s3_out.data := DontCare 390 s3_out.debug.isMMIO := s3_in.mmio 391 s3_out.debug.paddr := s3_in.paddr 392 s3_out.debug.vaddr := s3_in.vaddr 393 s3_out.debug.isPerfCnt := false.B 394 395 // Pipeline 396 // -------------------------------------------------------------------------------- 397 // stage x 398 // -------------------------------------------------------------------------------- 399 // delay TotalSelectCycles - 2 cycle(s) 400 val TotalDelayCycles = TotalSelectCycles - 2 401 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 402 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 403 val sx_in = Wire(Vec(TotalDelayCycles + 1, new MemExuOutput)) 404 405 // backward ready signal 406 s3_ready := sx_ready.head 407 for (i <- 0 until TotalDelayCycles + 1) { 408 if (i == 0) { 409 sx_valid(i) := s3_valid 410 sx_in(i) := s3_out 411 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 412 } else { 413 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 414 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 415 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 416 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 417 418 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 419 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 420 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 421 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 422 } 423 } 424 val sx_last_valid = sx_valid.takeRight(1).head 425 val sx_last_ready = sx_ready.takeRight(1).head 426 val sx_last_in = sx_in.takeRight(1).head 427 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 428 429 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) && isStore(sx_last_in.uop.fuType) 430 io.stout.bits := sx_last_in 431 432 io.debug_ls := DontCare 433 io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 434 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 435 436 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 437 XSDebug(cond, 438 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 439 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 440 p"op ${Binary(pipeline.uop.fuOpType)} " + 441 p"data ${Hexadecimal(pipeline.data)} " + 442 p"mask ${Hexadecimal(pipeline.mask)}\n" 443 ) 444 } 445 446 printPipeLine(s0_out, s0_valid, "S0") 447 printPipeLine(s1_out, s1_valid, "S1") 448 449 // perf cnt 450 XSPerfAccumulate("s0_in_valid", s0_valid) 451 XSPerfAccumulate("s0_in_fire", s0_fire) 452 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 453 XSPerfAccumulate("s0_addr_spec_success", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12)) 454 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12)) 455 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 456 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 457 458 XSPerfAccumulate("s1_in_valid", s1_valid) 459 XSPerfAccumulate("s1_in_fire", s1_fire) 460 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 461 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 462 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 463 // end 464}