xref: /XiangShan/src/test/scala/top/SimTop.scala (revision c6d439803a044ea209139672b25e35fe8d7f4aa0) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3*
4* XiangShan is licensed under Mulan PSL v2.
5* You can use this software according to the terms and conditions of the Mulan PSL v2.
6* You may obtain a copy of Mulan PSL v2 at:
7*          http://license.coscl.org.cn/MulanPSL2
8*
9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
12*
13* See the Mulan PSL v2 for more details.
14***************************************************************************************/
15
16package top
17
18import chipsalliance.rocketchip.config.{Config, Parameters}
19import chisel3.stage.ChiselGeneratorAnnotation
20import chisel3._
21import device.{AXI4RAMWrapper, UARTIO}
22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
23import utils.GTimer
24import xiangshan.{DebugOptions, DebugOptionsKey, PerfInfoIO}
25
26class LogCtrlIO extends Bundle {
27  val log_begin, log_end = Input(UInt(64.W))
28  val log_level = Input(UInt(64.W)) // a cpp uint
29}
30
31class SimTop(implicit p: Parameters) extends Module {
32  val debugOpts = p(DebugOptionsKey)
33  val useDRAMSim = debugOpts.UseDRAMSim
34
35  val l_soc = LazyModule(new XSTopWithoutDMA())
36  val soc = Module(l_soc.module)
37
38  val l_simMMIO = LazyModule(new SimMMIO(l_soc.peripheralNode.in.head._2))
39  val simMMIO = Module(l_simMMIO.module)
40  l_simMMIO.connectToSoC(l_soc)
41
42  if(!useDRAMSim){
43    val l_simAXIMem = LazyModule(new AXI4RAMWrapper(
44      l_soc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true
45    ))
46    val simAXIMem = Module(l_simAXIMem.module)
47    l_simAXIMem.connectToSoC(l_soc)
48  }
49
50  soc.io.clock := clock.asBool()
51  soc.io.reset := reset.asBool()
52  soc.io.extIntrs := simMMIO.io.interrupt.intrVec
53
54  val io = IO(new Bundle(){
55    val logCtrl = new LogCtrlIO
56    val perfInfo = new PerfInfoIO
57    val uart = new UARTIO
58    val memAXI = if(useDRAMSim) l_soc.memory.cloneType else null
59  })
60
61  simMMIO.io.uart <> io.uart
62
63  if(useDRAMSim){
64    io.memAXI <> l_soc.memory
65  }
66
67  if (debugOpts.EnableDebug || debugOpts.EnablePerfDebug) {
68    val timer = GTimer()
69    val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
70    ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
71    ExcitingUtils.addSource(timer, "logTimestamp")
72  }
73
74  if (debugOpts.EnablePerfDebug) {
75    val clean = io.perfInfo.clean
76    val dump = io.perfInfo.dump
77    ExcitingUtils.addSource(clean, "XSPERF_CLEAN")
78    ExcitingUtils.addSource(dump, "XSPERF_DUMP")
79  }
80
81  // Check and dispaly all source and sink connections
82  ExcitingUtils.fixConnections()
83  ExcitingUtils.checkAndDisplay()
84}
85
86object SimTop extends App {
87
88  override def main(args: Array[String]): Unit = {
89    val (config, firrtlOpts) = ArgParser.parse(args, fpga = false)
90    // generate verilog
91    XiangShanStage.execute(
92      firrtlOpts,
93      Seq(
94        ChiselGeneratorAnnotation(() => new SimTop()(config))
95      )
96    )
97  }
98}
99