1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VFAlu, VFMA, VFDivSqrt, VIAluFix, VIMacU, VIDiv, VPPU, VIPU, VSetRiWi, VSetRiWvf, VSetRvfWvf, VCVT} 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeFflags the $fu write fflags csr 26 * @param writeVxsat the $fu write vxsat csr 27 * @param dataBits the width of data in the $fu 28 * @param latency the latency of instuction executed in the $fu 29 * @param hasInputBuffer if the $fu has input buffer 30 * @param exceptionOut the $fu can produce these exception 31 * @param hasLoadError if the $fu has load error out 32 * @param flushPipe if the instuction executed in the $fu need flush out 33 * @param replayInst if the instuction executed in the $fu can replay in some condition 34 * @param trigger if the $fu need trigger out 35 * @param needSrcFrm if the $fu need float rounding mode signal 36 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 37 * @param immType the immediate type of this $fu 38 * @param vconfigWakeUp 39 * @param maskWakeUp 40 * 41 * @define fu function unit 42 */ 43case class FuConfig ( 44 name : String, 45 fuType : FuType.OHType, 46 fuGen : (Parameters, FuConfig) => FuncUnit, 47 srcData : Seq[Seq[DataConfig]], 48 piped : Boolean, 49 maybeBlock : Boolean = false, 50 writeIntRf : Boolean = false, 51 writeFpRf : Boolean = false, 52 writeVecRf : Boolean = false, 53 writeFakeIntRf: Boolean = false, 54 writeFflags : Boolean = false, 55 writeVxsat : Boolean = false, 56 dataBits : Int = 64, 57 latency : HasFuLatency = CertainLatency(0), 58 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 59 exceptionOut : Seq[Int] = Seq(), 60 hasLoadError : Boolean = false, 61 flushPipe : Boolean = false, 62 replayInst : Boolean = false, 63 trigger : Boolean = false, 64 needSrcFrm : Boolean = false, 65 needSrcVxrm : Boolean = false, 66 immType : Set[UInt] = Set(), 67 // vector 68 vconfigWakeUp : Boolean = false, 69 maskWakeUp : Boolean = false, 70) { 71 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 72 def needFpWen: Boolean = writeFpRf 73 def needVecWen: Boolean = writeVecRf 74 var vconfigIdx = -1 75 var maskSrcIdx = -1 76 if (vconfigWakeUp) { 77 vconfigIdx = getSpecialSrcIdx(VConfigData(), "when vconfigWakeUp is true, srcData must always contains VConfigData()") 78 } 79 if (maskWakeUp) { 80 maskSrcIdx = getSpecialSrcIdx(MaskSrcData(), "when maskWakeUp is true, srcData must always contains MaskSrcData()") 81 } 82 83 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 84 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 85 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 86 87 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 88 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 89 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 90 def numVfSrc : Int = srcData.map(_.count(x => VfRegSrcDataSet.contains(x))).fold(0)(_ max _) 91 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 92 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 93 94 def readFp: Boolean = numFpSrc > 0 95 96 def fuSel(uop: ExuInput): Bool = { 97 // Don't add more shit here!!! 98 // Todo: add new FuType to distinguish f2i, f2f 99 uop.fuType === this.fuType.U 100 } 101 102 /** 103 * params(i): data type set of the ith src port 104 * @return 105 */ 106 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 107 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 108 // make srcData is uniform sized to avoid exception when transpose 109 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 110 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 111 } 112 113 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 114 srcData 115 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 116 .filter(_.nonEmpty) 117 .map(_.get) 118 .toSet 119 } 120 121 def hasNoDataWB: Boolean = { 122 !(writeIntRf || writeFpRf || writeVecRf) 123 } 124 125 def getSrcMaxWidthVec = { 126 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 127 } 128 129 def genSrcDataVec: Seq[UInt] = { 130 getSrcMaxWidthVec.map(w => UInt(w.W)) 131 } 132 133 // csr's redirect is in its exception bundle 134 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh).contains(fuType) 135 136 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 137 138 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 139 140 // predict info 141 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 142 143 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 144 145 def needFPUCtrl: Boolean = { 146 import FuType._ 147 Seq(fmac, fDivSqrt, fmisc, i2f).contains(fuType) 148 } 149 150 def needVecCtrl: Boolean = { 151 import FuType._ 152 Seq(vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 153 } 154 155 def isMul: Boolean = fuType == FuType.mul 156 157 def isDiv: Boolean = fuType == FuType.div 158 159 def isCsr: Boolean = fuType == FuType.csr 160 161 def isFence: Boolean = fuType == FuType.fence 162 163 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 164 fuType == FuType.vppu || fuType == FuType.vipu || 165 fuType == FuType.vfalu || fuType == FuType.vfma || 166 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 167 fuType == FuType.vidiv 168 169 def isSta: Boolean = name.contains("sta") 170 171 def ckAlwaysEn: Boolean = isCsr || isFence || fuType == FuType.vfalu || 172 fuType == FuType.fmisc || fuType == FuType.div || 173 fuType == FuType.vfdiv || fuType == FuType.vidiv 174 175 /** 176 * Get index of special src data, like [[VConfigData]], [[MaskSrcData]] 177 * @param data [[DataConfig]] 178 * @param tips tips if get failed 179 * @return the index of special src data 180 */ 181 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 182 val srcIdxVec = srcData.map(x => x.indexOf(data)) 183 val idx0 = srcIdxVec.head 184 for (idx <- srcIdxVec) { 185 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 186 } 187 idx0 188 } 189 190 override def toString: String = { 191 var str = s"${this.name}: " 192 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 193 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 194 str += s"latency($latency)" 195 str += s"src($srcData)" 196 str 197 } 198} 199 200object FuConfig { 201 val JmpCfg: FuConfig = FuConfig ( 202 name = "jmp", 203 fuType = FuType.jmp, 204 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 205 srcData = Seq( 206 Seq(IntData()), // jal 207 ), 208 piped = true, 209 writeIntRf = true, 210 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 211 ) 212 213 val BrhCfg: FuConfig = FuConfig ( 214 name = "brh", 215 fuType = FuType.brh, 216 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 217 srcData = Seq( 218 Seq(IntData(), IntData()), 219 ), 220 piped = true, 221 immType = Set(SelImm.IMM_SB), 222 ) 223 224 val I2fCfg: FuConfig = FuConfig ( 225 name = "i2f", 226 FuType.i2f, 227 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 228 srcData = Seq( 229 Seq(IntData()), 230 ), 231 piped = true, 232 writeFpRf = true, 233 writeFflags = true, 234 latency = CertainLatency(2), 235 needSrcFrm = true, 236 ) 237 238 val I2vCfg: FuConfig = FuConfig ( 239 name = "i2v", 240 FuType.i2v, 241 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 242 srcData = Seq( 243 Seq(IntData(), IntData()), 244 ), 245 piped = true, 246 writeVecRf = true, 247 writeFpRf = true, 248 latency = CertainLatency(0), 249 dataBits = 128, 250 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 251 ) 252 253 val F2vCfg: FuConfig = FuConfig ( 254 name = "f2v", 255 FuType.f2v, 256 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 257 srcData = Seq( 258 Seq(FpData(), FpData()), 259 Seq(FpData()), 260 ), 261 piped = true, 262 writeVecRf = true, 263 latency = CertainLatency(0), 264 dataBits = 128, 265 ) 266 267 val CsrCfg: FuConfig = FuConfig ( 268 name = "csr", 269 fuType = FuType.csr, 270 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 271 srcData = Seq( 272 Seq(IntData()), 273 ), 274 piped = true, 275 writeIntRf = true, 276 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 277 flushPipe = true, 278 ) 279 280 val AluCfg: FuConfig = FuConfig ( 281 name = "alu", 282 fuType = FuType.alu, 283 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 284 srcData = Seq( 285 Seq(IntData(), IntData()), 286 ), 287 piped = true, 288 writeIntRf = true, 289 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 290 ) 291 292 val MulCfg: FuConfig = FuConfig ( 293 name = "mul", 294 fuType = FuType.mul, 295 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 296 srcData = Seq( 297 Seq(IntData(), IntData()), 298 ), 299 piped = true, 300 writeIntRf = true, 301 latency = CertainLatency(2), 302 ) 303 304 val DivCfg: FuConfig = FuConfig ( 305 name = "div", 306 fuType = FuType.div, 307 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 308 srcData = Seq( 309 Seq(IntData(), IntData()), 310 ), 311 piped = false, 312 writeIntRf = true, 313 latency = UncertainLatency(), 314 hasInputBuffer = (true, 4, true) 315 ) 316 317 val FenceCfg: FuConfig = FuConfig ( 318 name = "fence", 319 FuType.fence, 320 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 321 srcData = Seq( 322 Seq(IntData(), IntData()), 323 ), 324 piped = true, 325 latency = CertainLatency(0), 326 exceptionOut = Seq(illegalInstr), 327 flushPipe = true 328 ) 329 330 // Todo: split it to simple bitmap exu and complex bku 331 val BkuCfg: FuConfig = FuConfig ( 332 name = "bku", 333 fuType = FuType.bku, 334 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 335 srcData = Seq( 336 Seq(IntData(), IntData()), 337 ), 338 piped = true, 339 writeIntRf = true, 340 latency = CertainLatency(2), 341 ) 342 343 val VSetRvfWvfCfg: FuConfig = FuConfig( 344 name = "vsetrvfwvf", 345 fuType = FuType.vsetfwf, 346 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 347 srcData = Seq( 348 Seq(FpData(), FpData()), 349 ), 350 piped = true, 351 writeVecRf = true, 352 latency = CertainLatency(0), 353 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 354 ) 355 356 val VSetRiWvfCfg: FuConfig = FuConfig( 357 name = "vsetriwvf", 358 fuType = FuType.vsetiwf, 359 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 360 srcData = Seq( 361 Seq(IntData(), IntData()), 362 ), 363 piped = true, 364 writeVecRf = true, 365 latency = CertainLatency(0), 366 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 367 ) 368 369 val VSetRiWiCfg: FuConfig = FuConfig( 370 name = "vsetriwi", 371 fuType = FuType.vsetiwi, 372 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 373 srcData = Seq( 374 Seq(IntData(), IntData()), 375 ), 376 piped = true, 377 writeIntRf = true, 378 latency = CertainLatency(0), 379 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 380 ) 381 382 val FmacCfg: FuConfig = FuConfig ( 383 name = "fmac", 384 fuType = FuType.fmac, 385 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("FMac")), 386 srcData = Seq( 387 Seq(FpData(), FpData()), 388 Seq(FpData(), FpData(), FpData()), 389 ), 390 piped = false, 391 writeFpRf = true, 392 writeFflags = true, 393 latency = UncertainLatency(), 394 needSrcFrm = true, 395 ) 396 397 val F2iCfg: FuConfig = FuConfig ( 398 name = "f2i", 399 fuType = FuType.fmisc, 400 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToInt(cfg)(p).suggestName("F2i")), 401 srcData = Seq( 402 Seq(FpData(), FpData()), 403 Seq(FpData()), 404 ), 405 piped = true, 406 writeIntRf = true, 407 writeFflags = true, 408 latency = CertainLatency(2), 409 needSrcFrm = true, 410 ) 411 412 val F2fCfg: FuConfig = FuConfig ( 413 name = "f2f", 414 fuType = FuType.fmisc, 415 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FPToFP(cfg)(p).suggestName("F2f")), 416 srcData = Seq( 417 Seq(FpData(), FpData()), 418 Seq(FpData()), 419 ), 420 piped = true, 421 writeFpRf = true, 422 writeFflags = true, 423 latency = CertainLatency(2), 424 needSrcFrm = true, 425 ) 426 427 val FDivSqrtCfg: FuConfig = FuConfig ( 428 name = "fDivSqrt", 429 fuType = FuType.fDivSqrt, 430 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("FDivSqrt")), 431 srcData = Seq( 432 Seq(FpData(), FpData()), 433 ), 434 piped = false, 435 writeFpRf = true, 436 writeFflags = true, 437 latency = UncertainLatency(), 438 hasInputBuffer = (true, 8, true), 439 needSrcFrm = true, 440 ) 441 442 val LduCfg: FuConfig = FuConfig ( 443 name = "ldu", 444 fuType = FuType.ldu, 445 fuGen = null, // Todo 446 srcData = Seq( 447 Seq(IntData()), 448 ), 449 piped = false, // Todo: check it 450 writeIntRf = true, 451 writeFpRf = true, 452 latency = UncertainLatency(3), 453 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 454 flushPipe = true, 455 replayInst = true, 456 hasLoadError = true, 457 trigger = true, 458 immType = Set(SelImm.IMM_I), 459 ) 460 461 val StaCfg: FuConfig = FuConfig ( 462 name = "sta", 463 fuType = FuType.stu, 464 fuGen = null, // Todo 465 srcData = Seq( 466 Seq(IntData()), 467 ), 468 piped = false, 469 latency = UncertainLatency(), 470 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 471 trigger = true, 472 immType = Set(SelImm.IMM_S), 473 ) 474 475 val StdCfg: FuConfig = FuConfig ( 476 name = "std", 477 fuType = FuType.stu, 478 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 479 srcData = Seq( 480 Seq(IntData()), 481 Seq(FpData()), 482 ), 483 piped = true, 484 latency = CertainLatency(0) 485 ) 486 487 val HyldaCfg = FuConfig ( 488 name = "hylda", 489 fuType = FuType.ldu, 490 fuGen = null, // Todo 491 srcData = Seq( 492 Seq(IntData()), 493 ), 494 piped = false, // Todo: check it 495 writeIntRf = true, 496 writeFpRf = true, 497 latency = UncertainLatency(3), 498 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 499 flushPipe = true, 500 replayInst = true, 501 hasLoadError = true, 502 immType = Set(SelImm.IMM_I), 503 ) 504 505 val HystaCfg = FuConfig ( 506 name = "hysta", 507 fuType = FuType.stu, 508 fuGen = null, // Todo 509 srcData = Seq( 510 Seq(IntData()), 511 ), 512 piped = false, 513 latency = UncertainLatency(), 514 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 515 immType = Set(SelImm.IMM_S), 516 ) 517 518 val FakeHystaCfg = FuConfig ( 519 name = "hysta", 520 fuType = FuType.stu, 521 fuGen = null, // Todo 522 srcData = Seq(), 523 piped = false, 524 latency = UncertainLatency(), 525 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 526 immType = Set(), 527 ) 528 529 val MouCfg: FuConfig = FuConfig ( 530 name = "mou", 531 fuType = FuType.mou, 532 fuGen = null, // Todo 533 srcData = Seq( 534 Seq(IntData()), 535 ), 536 piped = false, // Todo: check it 537 writeFakeIntRf = true, 538 latency = UncertainLatency(), 539 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 540 trigger = true, 541 ) 542 543 val MoudCfg: FuConfig = FuConfig ( 544 name = "moud", 545 fuType = FuType.mou, 546 fuGen = null, // Todo 547 srcData = Seq( 548 Seq(IntData()), 549 ), 550 piped = true, 551 latency = CertainLatency(0), 552 ) 553 554 val VialuCfg = FuConfig ( 555 name = "vialuFix", 556 fuType = FuType.vialuF, 557 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 558 srcData = Seq( 559 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 560 ), 561 piped = true, 562 writeVecRf = true, 563 writeVxsat = true, 564 needSrcVxrm = true, 565 latency = CertainLatency(1), 566 vconfigWakeUp = true, 567 maskWakeUp = true, 568 dataBits = 128, 569 exceptionOut = Seq(illegalInstr), 570 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 571 ) 572 573 val VimacCfg = FuConfig ( 574 name = "vimac", 575 fuType = FuType.vimac, 576 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 577 srcData = Seq( 578 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 579 ), 580 piped = true, 581 writeVecRf = true, 582 writeVxsat = true, 583 needSrcVxrm = true, 584 latency = CertainLatency(2), 585 vconfigWakeUp = true, 586 maskWakeUp = true, 587 dataBits = 128, 588 exceptionOut = Seq(illegalInstr), 589 ) 590 591 val VidivCfg = FuConfig ( 592 name = "vidiv", 593 fuType = FuType.vidiv, 594 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 595 srcData = Seq( 596 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 597 ), 598 piped = false, 599 writeVecRf = true, 600 latency = UncertainLatency(), 601 vconfigWakeUp = true, 602 maskWakeUp = true, 603 dataBits = 128, 604 exceptionOut = Seq(illegalInstr), 605 ) 606 607 val VppuCfg = FuConfig ( 608 name = "vppu", 609 fuType = FuType.vppu, 610 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 611 srcData = Seq( 612 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 613 ), 614 piped = true, 615 writeVecRf = true, 616 latency = CertainLatency(2), 617 vconfigWakeUp = true, 618 maskWakeUp = true, 619 dataBits = 128, 620 exceptionOut = Seq(illegalInstr), 621 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS), 622 ) 623 624 val VipuCfg: FuConfig = FuConfig ( 625 name = "vipu", 626 fuType = FuType.vipu, 627 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 628 srcData = Seq( 629 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0 630 ), 631 piped = true, 632 writeIntRf = true, 633 writeVecRf = true, 634 latency = CertainLatency(2), 635 vconfigWakeUp = true, 636 maskWakeUp = true, 637 dataBits = 128, 638 exceptionOut = Seq(illegalInstr), 639 ) 640 641 val VfaluCfg = FuConfig ( 642 name = "vfalu", 643 fuType = FuType.vfalu, 644 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 645 srcData = Seq( 646 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 647 ), 648 piped = true, 649 writeVecRf = true, 650 writeFpRf = true, 651 writeIntRf = true, 652 writeFflags = true, 653 latency = CertainLatency(1), 654 vconfigWakeUp = true, 655 maskWakeUp = true, 656 dataBits = 128, 657 exceptionOut = Seq(illegalInstr), 658 needSrcFrm = true, 659 ) 660 661 val VfmaCfg = FuConfig ( 662 name = "vfma", 663 fuType = FuType.vfma, 664 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 665 srcData = Seq( 666 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 667 ), 668 piped = true, 669 writeVecRf = true, 670 writeFpRf = true, 671 writeFflags = true, 672 latency = CertainLatency(3), 673 vconfigWakeUp = true, 674 maskWakeUp = true, 675 dataBits = 128, 676 exceptionOut = Seq(illegalInstr), 677 needSrcFrm = true, 678 ) 679 680 val VfdivCfg = FuConfig( 681 name = "vfdiv", 682 fuType = FuType.vfdiv, 683 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 684 srcData = Seq( 685 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 686 ), 687 piped = false, 688 writeVecRf = true, 689 writeFpRf = true, 690 writeFflags = true, 691 latency = UncertainLatency(), 692 vconfigWakeUp = true, 693 maskWakeUp = true, 694 dataBits = 128, 695 exceptionOut = Seq(illegalInstr), 696 needSrcFrm = true, 697 ) 698 699 val VfcvtCfg = FuConfig( 700 name = "vfcvt", 701 fuType = FuType.vfcvt, 702 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 703 srcData = Seq( 704 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), // vs1, vs2, vd_old, v0, vtype&vl 705 ), 706 piped = true, 707 writeVecRf = true, 708 writeFpRf = true, 709 writeIntRf = true, 710 writeFflags = true, 711 latency = CertainLatency(2), 712 vconfigWakeUp = true, 713 maskWakeUp = true, 714 dataBits = 128, 715 exceptionOut = Seq(illegalInstr), 716 needSrcFrm = true, 717 ) 718 719 720 val VlduCfg: FuConfig = FuConfig ( 721 name = "vldu", 722 fuType = FuType.vldu, 723 fuGen = null, 724 srcData = Seq( 725 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 726 ), 727 piped = false, // Todo: check it 728 writeVecRf = true, 729 latency = UncertainLatency(), 730 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 731 flushPipe = true, 732 replayInst = true, 733 hasLoadError = true, 734 vconfigWakeUp = true, 735 maskWakeUp = true, 736 dataBits = 128, 737 ) 738 739 val VstuCfg: FuConfig = FuConfig ( 740 name = "vstu", 741 fuType = FuType.vstu, 742 fuGen = null, 743 srcData = Seq( 744 Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()), //vs1, vs2, vd_old, v0, vconfig 745 ), 746 piped = false, 747 writeVecRf = false, 748 latency = UncertainLatency(), 749 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault), 750 flushPipe = true, 751 replayInst = true, 752 hasLoadError = true, 753 vconfigWakeUp = true, 754 maskWakeUp = true, 755 dataBits = 128, 756 ) 757 758 def allConfigs = Seq( 759 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 760 FmacCfg, F2iCfg, F2fCfg, FDivSqrtCfg, LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, 761 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 762 ) 763 764 def VecArithFuConfigs = Seq( 765 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 766 ) 767} 768 769