xref: /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala (revision 5c1681d0ba1d64dd3c2a4b6eae3703364c554743) 
1package xiangshan.backend.fu.vector
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util._
6import xiangshan.XSCoreParamsKey
7import xiangshan.backend.decode.isa.bitfield.InstVType
8import xiangshan.backend.fu.VtypeStruct
9
10object Bundles {
11
12  /**
13    * vtype bundle, should not used as csr reg
14    */
15  class VType(implicit p: Parameters) extends Bundle {
16    val illegal = Bool()
17    val vma     = Bool()
18    val vta     = Bool()
19    val vsew    = VSew()
20    val vlmul   = VLmul()
21  }
22
23  object VType {
24    def apply()(implicit p: Parameters) : VType = {
25      new VType
26    }
27
28    def fromInstVType(instVType: InstVType)(implicit p: Parameters) : VType = {
29      val res = Wire(VType())
30      res.vma   := instVType.vma
31      res.vta   := instVType.vta
32      res.vsew  := instVType.vsew(VSew.width - 1, 0)
33      res.vlmul := instVType.vlmul
34      res.illegal := false.B // Todo: add illegal check function
35      res
36    }
37
38    def fromVtypeStruct(vtypeStruct: VtypeStruct)(implicit p: Parameters): VType = {
39      val res = Wire(VType())
40      res.illegal := vtypeStruct.vill
41      res.vma := vtypeStruct.vma
42      res.vta := vtypeStruct.vta
43      res.vsew := vtypeStruct.vsew(VSew.width - 1, 0)
44      res.vlmul := vtypeStruct.vlmul
45      res
46    }
47
48    def toVtypeStruct(vtype: VType)(implicit p: Parameters) : VtypeStruct = {
49      val res = WireInit(0.U.asTypeOf(new VtypeStruct))
50      res.vill := vtype.illegal
51      res.vma := vtype.vma
52      res.vta := vtype.vta
53      res.vsew := Cat(0.U(1.W), vtype.vsew)
54      res.vlmul := vtype.vlmul
55      res
56    }
57  }
58
59  class VConfig(implicit p: Parameters) extends Bundle {
60    val vl    = Vl()
61    val vtype = new VType
62  }
63
64  object VConfig {
65    def apply()(implicit p: Parameters) : VConfig = {
66      new VConfig()
67    }
68  }
69
70  def mu: UInt = 0.U(1.W)
71  def ma: UInt = 1.U(1.W)
72  def tu: UInt = 0.U(1.W)
73  def ta: UInt = 1.U(1.W)
74
75  object VSew {
76    def apply(): UInt = UInt(width.W)
77
78    def width = 2 // modify it when support more vector data width
79
80    def e8  : UInt = "b000".U(width.W)
81    def e16 : UInt = "b001".U(width.W)
82    def e32 : UInt = "b010".U(width.W)
83    def e64 : UInt = "b011".U(width.W)
84
85    def reserved: BitPat = BitPat("b1??")
86
87    def isReserved(sew: UInt) : Bool = {
88      require(sew.getWidth >= 2 && sew.getWidth <= 3)
89      if (sew.getWidth == 3) {
90        sew === reserved
91      } else {
92        false.B
93      }
94    }
95  }
96
97  object VLmul {
98    def apply(): UInt = UInt(width.W)
99
100    def width = 3
101
102    def m1  : UInt = "b000".U(width.W)
103    def m2  : UInt = "b001".U(width.W)
104    def m4  : UInt = "b010".U(width.W)
105    def m8  : UInt = "b011".U(width.W)
106    def mf2 : UInt = "b111".U(width.W)
107    def mf4 : UInt = "b110".U(width.W)
108    def mf8 : UInt = "b101".U(width.W)
109
110    def reserved: BitPat = BitPat("b100")
111
112    def isReserved(vlmul: UInt) : Bool = {
113      require(vlmul.getWidth == 3)
114      vlmul === reserved
115    }
116  }
117
118  object Vl {
119    def apply()(implicit p: Parameters): UInt = UInt(width.W)
120
121    def width(implicit p: Parameters) = p(XSCoreParamsKey).vlWidth
122  }
123}
124