1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend.rename 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import xiangshan.backend.roq.RoqPtr 24import xiangshan.backend.dispatch.PreDispatchInfo 25 26class RenameBypassInfo(implicit p: Parameters) extends XSBundle { 27 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 28 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 29 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 30 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 31 val move_eliminated_src1 = Vec(RenameWidth-1, Bool()) 32 val move_eliminated_src2 = Vec(RenameWidth-1, Bool()) 33} 34 35class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 36 val io = IO(new Bundle() { 37 val redirect = Flipped(ValidIO(new Redirect)) 38 val flush = Input(Bool()) 39 val roqCommits = Flipped(new RoqCommitIO) 40 // from decode buffer 41 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 42 // to dispatch1 43 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 44 val renameBypass = Output(new RenameBypassInfo) 45 val dispatchInfo = Output(new PreDispatchInfo) 46 val csrCtrl = Flipped(new CustomCSRCtrlIO) 47 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 48 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 49 }) 50 51 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 52 XSInfo( 53 in.valid && in.ready, 54 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 55 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 56 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 57 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 58 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 59 p"old_pdest:${out.bits.old_pdest} " + 60 p"out v:${out.valid} r:${out.ready}\n" 61 ) 62 } 63 64 for((x,y) <- io.in.zip(io.out)){ 65 printRenameInfo(x, y) 66 } 67 68 val intFreeList, fpFreeList = Module(new FreeList).io 69 val intRat = Module(new RenameTable(float = false)).io 70 val fpRat = Module(new RenameTable(float = true)).io 71 val allPhyResource = Seq((intRat, intFreeList, false), (fpRat, fpFreeList, true)) 72 intRat.debug_rdata <> io.debug_int_rat 73 fpRat.debug_rdata <> io.debug_fp_rat 74 75 allPhyResource.map{ case (rat, freelist, _) => 76 rat.redirect := io.redirect.valid 77 rat.flush := io.flush 78 rat.walkWen := io.roqCommits.isWalk 79 freelist.redirect := io.redirect.valid 80 freelist.flush := io.flush 81 freelist.walk.valid := io.roqCommits.isWalk 82 } 83 val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk 84 85 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 86 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 87 } 88 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 89 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 90 } 91 fpFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(true, i)}) 92 intFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(false, i)}) 93 // walk has higher priority than allocation and thus we don't use isWalk here 94 fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready 95 intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready 96 97 // speculatively assign the instruction with an roqIdx 98 val validCount = PopCount(io.in.map(_.valid)) 99 val roqIdxHead = RegInit(0.U.asTypeOf(new RoqPtr)) 100 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 101 val roqIdxHeadNext = Mux(io.flush, 102 0.U.asTypeOf(new RoqPtr), 103 Mux(io.redirect.valid, 104 io.redirect.bits.roqIdx, 105 Mux(lastCycleMisprediction, 106 roqIdxHead + 1.U, 107 Mux(canOut, roqIdxHead + validCount, roqIdxHead)) 108 ) 109 ) 110 roqIdxHead := roqIdxHeadNext 111 112 /** 113 * Rename: allocate free physical register and update rename table 114 */ 115 val uops = Wire(Vec(RenameWidth, new MicroOp)) 116 117 uops.foreach( uop => { 118// uop.brMask := DontCare 119// uop.brTag := DontCare 120 uop.srcState(0) := DontCare 121 uop.srcState(1) := DontCare 122 uop.srcState(2) := DontCare 123 uop.roqIdx := DontCare 124 uop.diffTestDebugLrScValid := DontCare 125 uop.debugInfo := DontCare 126 uop.lqIdx := DontCare 127 uop.sqIdx := DontCare 128 }) 129 130 val needFpDest = Wire(Vec(RenameWidth, Bool())) 131 val needIntDest = Wire(Vec(RenameWidth, Bool())) 132 val hasValid = Cat(io.in.map(_.valid)).orR 133 for (i <- 0 until RenameWidth) { 134 uops(i).cf := io.in(i).bits.cf 135 uops(i).ctrl := io.in(i).bits.ctrl 136 137 val inValid = io.in(i).valid 138 139 // alloc a new phy reg 140 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 141 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 142 fpFreeList.req.allocReqs(i) := needFpDest(i) 143 intFreeList.req.allocReqs(i) := needIntDest(i) 144 145 io.in(i).ready := !hasValid || canOut 146 147 // do checkpoints when a branch inst come 148 // for(fl <- Seq(fpFreeList, intFreeList)){ 149 // fl.cpReqs(i).valid := inValid 150 // fl.cpReqs(i).bits := io.in(i).bits.brTag 151 // } 152 153 uops(i).pdest := Mux(needIntDest(i), 154 intFreeList.req.pdests(i), 155 Mux( 156 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 157 0.U, fpFreeList.req.pdests(i) 158 ) 159 ) 160 161 uops(i).roqIdx := roqIdxHead + i.U 162 163 io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk 164 io.out(i).bits := uops(i) 165 166 // write speculative rename table 167 allPhyResource.map{ case (rat, freelist, _) => 168 val specWen = freelist.req.allocReqs(i) && freelist.req.canAlloc && freelist.req.doAlloc && !io.roqCommits.isWalk 169 170 rat.specWritePorts(i).wen := specWen 171 rat.specWritePorts(i).addr := uops(i).ctrl.ldest 172 rat.specWritePorts(i).wdata := freelist.req.pdests(i) 173 174 freelist.deallocReqs(i) := specWen 175 } 176 177 // read rename table 178 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 179 val rat = if(fp) fpRat else intRat 180 val srcCnt = lsrcList.size 181 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 182 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 183 for(k <- 0 until srcCnt+1){ 184 val rportIdx = i * (srcCnt+1) + k 185 if(k != srcCnt){ 186 rat.readPorts(rportIdx).addr := lsrcList(k) 187 psrcVec(k) := rat.readPorts(rportIdx).rdata 188 } else { 189 rat.readPorts(rportIdx).addr := ldest 190 old_pdest := rat.readPorts(rportIdx).rdata 191 } 192 } 193 (psrcVec, old_pdest) 194 } 195 val lsrcList = List(uops(i).ctrl.lsrc(0), uops(i).ctrl.lsrc(1), uops(i).ctrl.lsrc(2)) 196 val ldest = uops(i).ctrl.ldest 197 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 198 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 199 uops(i).psrc(0) := Mux(uops(i).ctrl.srcType(0) === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 200 uops(i).psrc(1) := Mux(uops(i).ctrl.srcType(1) === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 201 uops(i).psrc(2) := fpPhySrcVec(2) 202 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 203 } 204 205 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 206 // Instead, we determine whether there're some dependences between the valid instructions. 207 for (i <- 1 until RenameWidth) { 208 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 209 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.srcType(0) === SrcType.fp 210 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.srcType(0) === SrcType.reg 211 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(0) 212 }).reverse) 213 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 214 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.srcType(1) === SrcType.fp 215 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.srcType(1) === SrcType.reg 216 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(1) 217 }).reverse) 218 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 219 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.srcType(2) === SrcType.fp 220 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.srcType(2) === SrcType.reg 221 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(2) 222 }).reverse) 223 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 224 val fpMatch = needFpDest(j) && needFpDest(i) 225 val intMatch = needIntDest(j) && needIntDest(i) 226 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 227 }).reverse) 228 io.renameBypass.move_eliminated_src1(i-1) := 229 // the producer move instruction writes to non-zero register 230 io.in(i-1).bits.ctrl.isMove && io.in(i-1).bits.ctrl.ldest =/= 0.U && 231 // the consumer instruction uses the move's destination register 232 io.in(i).bits.ctrl.srcType(0) === SrcType.reg && io.in(i).bits.ctrl.lsrc(0) === io.in(i-1).bits.ctrl.ldest && 233 // CSR control (by srnctl) 234 io.csrCtrl.move_elim_enable 235 io.renameBypass.move_eliminated_src2(i-1) := 236 // the producer move instruction writes to non-zero register 237 io.in(i-1).bits.ctrl.isMove && io.in(i-1).bits.ctrl.ldest =/= 0.U && 238 // the consumer instruction uses the move's destination register 239 io.in(i).bits.ctrl.srcType(1) === SrcType.reg && io.in(i).bits.ctrl.lsrc(1) === io.in(i-1).bits.ctrl.ldest && 240 // CSR control (by srnctl) 241 io.csrCtrl.move_elim_enable 242 } 243 244 val isLs = VecInit(uops.map(uop => FuType.isLoadStore(uop.ctrl.fuType))) 245 val isStore = VecInit(uops.map(uop => FuType.isStoreExu(uop.ctrl.fuType))) 246 val isAMO = VecInit(uops.map(uop => FuType.isAMO(uop.ctrl.fuType))) 247 io.dispatchInfo.lsqNeedAlloc := VecInit((0 until RenameWidth).map(i => 248 Mux(isLs(i), Mux(isStore(i) && !isAMO(i), 2.U, 1.U), 0.U))) 249 250 /** 251 * Instructions commit: update freelist and rename table 252 */ 253 for (i <- 0 until CommitWidth) { 254 if (i >= RenameWidth) { 255 allPhyResource.map{ case (rat, _, _) => 256 rat.specWritePorts(i).wen := false.B 257 rat.specWritePorts(i).addr := DontCare 258 rat.specWritePorts(i).wdata := DontCare 259 } 260 } 261 262 allPhyResource.map{ case (rat, freelist, fp) => 263 // walk back write 264 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 265 266 when (commitDestValid && io.roqCommits.isWalk) { 267 rat.specWritePorts(i).wen := true.B 268 rat.specWritePorts(i).addr := io.roqCommits.info(i).ldest 269 rat.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 270 XSInfo({if(fp) p"fp" else p"int "} + p"walk: " + 271 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n") 272 } 273 274 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 275 rat.archWritePorts(i).addr := io.roqCommits.info(i).ldest 276 rat.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 277 278 XSInfo(rat.archWritePorts(i).wen, 279 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 280 p" pdest:${rat.archWritePorts(i).wdata}\n" 281 ) 282 283 freelist.deallocReqs(i) := rat.archWritePorts(i).wen 284 freelist.deallocPregs(i) := io.roqCommits.info(i).old_pdest 285 } 286 } 287 288 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 289 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 290 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 291 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk) 292 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk) 293 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.req.canAlloc && !intFreeList.req.canAlloc && !io.roqCommits.isWalk) 294 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && io.roqCommits.isWalk) 295 296 297} 298