1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import xiangshan.frontend.icache.ICacheParameters 43 44class BaseConfig(n: Int) extends Config((site, here, up) => { 45 case XLen => 64 46 case DebugOptionsKey => DebugOptions() 47 case SoCParamsKey => SoCParameters() 48 case PMParameKey => PMParameters() 49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 51 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 52 case JtagDTMKey => JtagDTMKey 53 case MaxHartIdBits => 2 54 case EnableJtag => true.B 55}) 56 57// Synthesizable minimal XiangShan 58// * It is still an out-of-order, super-scalaer arch 59// * L1 cache included 60// * L2 cache NOT included 61// * L3 cache included 62class MinimalConfig(n: Int = 1) extends Config( 63 new BaseConfig(n).alter((site, here, up) => { 64 case XSTileKey => up(XSTileKey).map( 65 _.copy( 66 DecodeWidth = 6, 67 RenameWidth = 6, 68 CommitWidth = 6, 69 FetchWidth = 4, 70 VirtualLoadQueueSize = 24, 71 LoadQueueRARSize = 16, 72 LoadQueueRAWSize = 12, 73 LoadQueueReplaySize = 24, 74 LoadUncacheBufferSize = 8, 75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 76 RollbackGroupSize = 8, 77 StoreQueueSize = 20, 78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 79 StoreQueueForwardWithMask = true, 80 RobSize = 48, 81 RabSize = 96, 82 FtqSize = 8, 83 IBufSize = 24, 84 IBufNBank = 6, 85 StoreBufferSize = 4, 86 StoreBufferThreshold = 3, 87 IssueQueueSize = 8, 88 IssueQueueCompEntrySize = 4, 89 dpParams = DispatchParameters( 90 IntDqSize = 12, 91 FpDqSize = 12, 92 LsDqSize = 12, 93 IntDqDeqWidth = 8, 94 FpDqDeqWidth = 4, 95 LsDqDeqWidth = 6 96 ), 97 intPreg = IntPregParams( 98 numEntries = 64, 99 numRead = None, 100 numWrite = None, 101 ), 102 vfPreg = VfPregParams( 103 numEntries = 160, 104 numRead = None, 105 numWrite = None, 106 ), 107 icacheParameters = ICacheParameters( 108 nSets = 64, // 16KB ICache 109 tagECC = Some("parity"), 110 dataECC = Some("parity"), 111 replacer = Some("setplru"), 112 nMissEntries = 2, 113 nReleaseEntries = 1, 114 nProbeEntries = 2, 115 // fdip 116 enableICachePrefetch = true, 117 prefetchToL1 = false, 118 ), 119 dcacheParametersOpt = Some(DCacheParameters( 120 nSets = 64, // 32KB DCache 121 nWays = 8, 122 tagECC = Some("secded"), 123 dataECC = Some("secded"), 124 replacer = Some("setplru"), 125 nMissEntries = 4, 126 nProbeEntries = 4, 127 nReleaseEntries = 8, 128 nMaxPrefetchEntry = 2, 129 )), 130 EnableBPD = false, // disable TAGE 131 EnableLoop = false, 132 itlbParameters = TLBParameters( 133 name = "itlb", 134 fetchi = true, 135 useDmode = false, 136 NWays = 4, 137 ), 138 ldtlbParameters = TLBParameters( 139 name = "ldtlb", 140 NWays = 4, 141 partialStaticPMP = true, 142 outsideRecvFlush = true, 143 outReplace = false, 144 lgMaxSize = 4 145 ), 146 sttlbParameters = TLBParameters( 147 name = "sttlb", 148 NWays = 4, 149 partialStaticPMP = true, 150 outsideRecvFlush = true, 151 outReplace = false, 152 lgMaxSize = 4 153 ), 154 hytlbParameters = TLBParameters( 155 name = "hytlb", 156 NWays = 4, 157 partialStaticPMP = true, 158 outsideRecvFlush = true, 159 outReplace = false, 160 lgMaxSize = 4 161 ), 162 pftlbParameters = TLBParameters( 163 name = "pftlb", 164 NWays = 4, 165 partialStaticPMP = true, 166 outsideRecvFlush = true, 167 outReplace = false, 168 lgMaxSize = 4 169 ), 170 btlbParameters = TLBParameters( 171 name = "btlb", 172 NWays = 4, 173 ), 174 l2tlbParameters = L2TLBParameters( 175 l1Size = 4, 176 l2nSets = 4, 177 l2nWays = 4, 178 l3nSets = 4, 179 l3nWays = 8, 180 spSize = 2, 181 ), 182 L2CacheParamsOpt = Some(L2Param( 183 name = "L2", 184 ways = 8, 185 sets = 128, 186 echoField = Seq(huancun.DirtyField()), 187 prefetch = None 188 )), 189 L2NBanks = 2, 190 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 191 ) 192 ) 193 case SoCParamsKey => 194 val tiles = site(XSTileKey) 195 up(SoCParamsKey).copy( 196 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 197 sets = 1024, 198 inclusive = false, 199 clientCaches = tiles.map{ core => 200 val clientDirBytes = tiles.map{ t => 201 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 202 }.sum 203 val l2params = core.L2CacheParamsOpt.get.toCacheParams 204 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 205 }, 206 simulation = !site(DebugOptionsKey).FPGAPlatform, 207 prefetch = None 208 )), 209 L3NBanks = 1 210 ) 211 }) 212) 213 214// Non-synthesizable MinimalConfig, for fast simulation only 215class MinimalSimConfig(n: Int = 1) extends Config( 216 new MinimalConfig(n).alter((site, here, up) => { 217 case XSTileKey => up(XSTileKey).map(_.copy( 218 dcacheParametersOpt = None, 219 softPTW = true 220 )) 221 case SoCParamsKey => up(SoCParamsKey).copy( 222 L3CacheParamsOpt = None 223 ) 224 }) 225) 226 227class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 228 case XSTileKey => 229 val sets = n * 1024 / ways / 64 230 up(XSTileKey).map(_.copy( 231 dcacheParametersOpt = Some(DCacheParameters( 232 nSets = sets, 233 nWays = ways, 234 tagECC = Some("secded"), 235 dataECC = Some("secded"), 236 replacer = Some("setplru"), 237 nMissEntries = 16, 238 nProbeEntries = 8, 239 nReleaseEntries = 18, 240 nMaxPrefetchEntry = 6, 241 )) 242 )) 243}) 244 245class WithNKBL2 246( 247 n: Int, 248 ways: Int = 8, 249 inclusive: Boolean = true, 250 banks: Int = 1 251) extends Config((site, here, up) => { 252 case XSTileKey => 253 require(inclusive, "L2 must be inclusive") 254 val upParams = up(XSTileKey) 255 val l2sets = n * 1024 / banks / ways / 64 256 upParams.map(p => p.copy( 257 L2CacheParamsOpt = Some(L2Param( 258 name = "L2", 259 ways = ways, 260 sets = l2sets, 261 clientCaches = Seq(L1Param( 262 "dcache", 263 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 264 ways = p.dcacheParametersOpt.get.nWays + 2, 265 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 266 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)) 267 )), 268 reqField = Seq(utility.ReqSourceField()), 269 echoField = Seq(huancun.DirtyField()), 270 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 271 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 272 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 273 )), 274 L2NBanks = banks 275 )) 276}) 277 278class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 279 case SoCParamsKey => 280 val sets = n * 1024 / banks / ways / 64 281 val tiles = site(XSTileKey) 282 val clientDirBytes = tiles.map{ t => 283 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 284 }.sum 285 up(SoCParamsKey).copy( 286 L3NBanks = banks, 287 L3CacheParamsOpt = Some(HCCacheParameters( 288 name = "L3", 289 level = 3, 290 ways = ways, 291 sets = sets, 292 inclusive = inclusive, 293 clientCaches = tiles.map{ core => 294 val l2params = core.L2CacheParamsOpt.get.toCacheParams 295 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 296 }, 297 enablePerf = true, 298 ctrl = Some(CacheCtrl( 299 address = 0x39000000, 300 numCores = tiles.size 301 )), 302 reqField = Seq(utility.ReqSourceField()), 303 sramClkDivBy2 = true, 304 sramDepthDiv = 4, 305 tagECC = Some("secded"), 306 dataECC = Some("secded"), 307 simulation = !site(DebugOptionsKey).FPGAPlatform, 308 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 309 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 310 )) 311 ) 312}) 313 314class WithL3DebugConfig extends Config( 315 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 316) 317 318class MinimalL3DebugConfig(n: Int = 1) extends Config( 319 new WithL3DebugConfig ++ new MinimalConfig(n) 320) 321 322class DefaultL3DebugConfig(n: Int = 1) extends Config( 323 new WithL3DebugConfig ++ new BaseConfig(n) 324) 325 326class WithFuzzer extends Config((site, here, up) => { 327 case DebugOptionsKey => up(DebugOptionsKey).copy( 328 EnablePerfDebug = false, 329 ) 330 case SoCParamsKey => up(SoCParamsKey).copy( 331 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 332 enablePerf = false, 333 )), 334 ) 335 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 336 p.copy( 337 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 338 enablePerf = false, 339 )), 340 ) 341 } 342}) 343 344class MinimalAliasDebugConfig(n: Int = 1) extends Config( 345 new WithNKBL3(512, inclusive = false) ++ 346 new WithNKBL2(256, inclusive = true) ++ 347 new WithNKBL1D(128) ++ 348 new MinimalConfig(n) 349) 350 351class MediumConfig(n: Int = 1) extends Config( 352 new WithNKBL3(4096, inclusive = false, banks = 4) 353 ++ new WithNKBL2(512, inclusive = true) 354 ++ new WithNKBL1D(128) 355 ++ new BaseConfig(n) 356) 357 358class FuzzConfig(dummy: Int = 0) extends Config( 359 new WithFuzzer 360 ++ new DefaultConfig(1) 361) 362 363class DefaultConfig(n: Int = 1) extends Config( 364 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 365 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 366 ++ new WithNKBL1D(64, ways = 4) 367 ++ new BaseConfig(n) 368) 369