1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan 17 18import chipsalliance.rocketchip.config.{Field, Parameters} 19import chisel3._ 20import chisel3.util._ 21import xiangshan.backend.exu._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.dispatch.DispatchParameters 25import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 26import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 27 28case object XSCoreParamsKey extends Field[XSCoreParameters] 29 30case class XSCoreParameters 31( 32 HasPrefetch: Boolean = false, 33 HartId: Int = 0, 34 XLEN: Int = 64, 35 HasMExtension: Boolean = true, 36 HasCExtension: Boolean = true, 37 HasDiv: Boolean = true, 38 HasICache: Boolean = true, 39 HasDCache: Boolean = true, 40 AddrBits: Int = 64, 41 VAddrBits: Int = 39, 42 PAddrBits: Int = 40, 43 HasFPU: Boolean = true, 44 FetchWidth: Int = 8, 45 EnableBPU: Boolean = true, 46 EnableBPD: Boolean = true, 47 EnableRAS: Boolean = true, 48 EnableLB: Boolean = false, 49 EnableLoop: Boolean = true, 50 EnableSC: Boolean = true, 51 EnbaleTlbDebug: Boolean = false, 52 EnableJal: Boolean = false, 53 EnableUBTB: Boolean = true, 54 HistoryLength: Int = 64, 55 BtbSize: Int = 2048, 56 JbtacSize: Int = 1024, 57 JbtacBanks: Int = 8, 58 RasSize: Int = 16, 59 CacheLineSize: Int = 512, 60 UBtbWays: Int = 16, 61 BtbWays: Int = 2, 62 63 EnableL1plusPrefetcher: Boolean = true, 64 IBufSize: Int = 48, 65 DecodeWidth: Int = 6, 66 RenameWidth: Int = 6, 67 CommitWidth: Int = 6, 68 BrqSize: Int = 32, 69 FtqSize: Int = 48, 70 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 71 IssQueSize: Int = 16, 72 NRPhyRegs: Int = 160, 73 NRIntReadPorts: Int = 14, 74 NRIntWritePorts: Int = 8, 75 NRFpReadPorts: Int = 14, 76 NRFpWritePorts: Int = 8, 77 LoadQueueSize: Int = 64, 78 StoreQueueSize: Int = 48, 79 RoqSize: Int = 192, 80 dpParams: DispatchParameters = DispatchParameters( 81 IntDqSize = 16, 82 FpDqSize = 16, 83 LsDqSize = 16, 84 IntDqDeqWidth = 4, 85 FpDqDeqWidth = 4, 86 LsDqDeqWidth = 4 87 ), 88 exuParameters: ExuParameters = ExuParameters( 89 JmpCnt = 1, 90 AluCnt = 4, 91 MulCnt = 0, 92 MduCnt = 2, 93 FmacCnt = 4, 94 FmiscCnt = 2, 95 FmiscDivSqrtCnt = 0, 96 LduCnt = 2, 97 StuCnt = 2 98 ), 99 LoadPipelineWidth: Int = 2, 100 StorePipelineWidth: Int = 2, 101 StoreBufferSize: Int = 16, 102 StoreBufferThreshold: Int = 7, 103 RefillSize: Int = 512, 104 TlbEntrySize: Int = 32, 105 TlbSPEntrySize: Int = 4, 106 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 107 PtwSPEntrySize: Int = 16, 108 PtwL1EntrySize: Int = 16, 109 PtwL2EntrySize: Int = 2048, //(256 * 8) 110 PtwMissQueueSize: Int = 8, 111 NumPerfCounters: Int = 16, 112 icacheParameters: ICacheParameters = ICacheParameters( 113 tagECC = Some("parity"), 114 dataECC = Some("parity"), 115 replacer = Some("setplru"), 116 nMissEntries = 2 117 ), 118 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 119 tagECC = Some("secded"), 120 dataECC = Some("secded"), 121 replacer = Some("setplru"), 122 nMissEntries = 8 123 ), 124 dcacheParameters: DCacheParameters = DCacheParameters( 125 tagECC = Some("secded"), 126 dataECC = Some("secded"), 127 replacer = Some("setplru"), 128 nMissEntries = 16, 129 nProbeEntries = 16, 130 nReleaseEntries = 16, 131 nStoreReplayEntries = 16 132 ), 133 L2Size: Int = 512 * 1024, // 512KB 134 L2NWays: Int = 8, 135 useFakePTW: Boolean = false, 136 useFakeDCache: Boolean = false, 137 useFakeL1plusCache: Boolean = false, 138 useFakeL2Cache: Boolean = false 139){ 140 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 141 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 142 143 val intExuConfigs = JumpExeUnitCfg +: ( 144 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) ++ 145 Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) 146 ) 147 148 val fpExuConfigs = 149 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 150 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 151 152 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 153} 154 155case object DebugOptionsKey extends Field[DebugOptions] 156 157case class DebugOptions 158( 159 FPGAPlatform: Boolean = true, 160 EnableDebug: Boolean = true, 161 EnablePerfDebug: Boolean = true, 162 UseDRAMSim: Boolean = false 163) 164 165trait HasXSParameter { 166 167 implicit val p: Parameters 168 169 val coreParams = p(XSCoreParamsKey) 170 val env = p(DebugOptionsKey) 171 172 val XLEN = coreParams.XLEN 173 val hardId = coreParams.HartId 174 val minFLen = 32 175 val fLen = 64 176 def xLen = XLEN 177 178 val HasMExtension = coreParams.HasMExtension 179 val HasCExtension = coreParams.HasCExtension 180 val HasDiv = coreParams.HasDiv 181 val HasIcache = coreParams.HasICache 182 val HasDcache = coreParams.HasDCache 183 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 184 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 185 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 186 val AddrBytes = AddrBits / 8 // unused 187 val DataBits = XLEN 188 val DataBytes = DataBits / 8 189 val HasFPU = coreParams.HasFPU 190 val FetchWidth = coreParams.FetchWidth 191 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 192 val EnableBPU = coreParams.EnableBPU 193 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 194 val EnableRAS = coreParams.EnableRAS 195 val EnableLB = coreParams.EnableLB 196 val EnableLoop = coreParams.EnableLoop 197 val EnableSC = coreParams.EnableSC 198 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 199 val HistoryLength = coreParams.HistoryLength 200 val BtbSize = coreParams.BtbSize 201 // val BtbWays = 4 202 val BtbBanks = PredictWidth 203 // val BtbSets = BtbSize / BtbWays 204 val JbtacSize = coreParams.JbtacSize 205 val JbtacBanks = coreParams.JbtacBanks 206 val RasSize = coreParams.RasSize 207 val CacheLineSize = coreParams.CacheLineSize 208 val CacheLineHalfWord = CacheLineSize / 16 209 val ExtHistoryLength = HistoryLength + 64 210 val UBtbWays = coreParams.UBtbWays 211 val BtbWays = coreParams.BtbWays 212 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 213 val IBufSize = coreParams.IBufSize 214 val DecodeWidth = coreParams.DecodeWidth 215 val RenameWidth = coreParams.RenameWidth 216 val CommitWidth = coreParams.CommitWidth 217 val BrqSize = coreParams.BrqSize 218 val FtqSize = coreParams.FtqSize 219 val IssQueSize = coreParams.IssQueSize 220 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 221 val BrTagWidth = log2Up(BrqSize) 222 val NRPhyRegs = coreParams.NRPhyRegs 223 val PhyRegIdxWidth = log2Up(NRPhyRegs) 224 val RoqSize = coreParams.RoqSize 225 val LoadQueueSize = coreParams.LoadQueueSize 226 val StoreQueueSize = coreParams.StoreQueueSize 227 val dpParams = coreParams.dpParams 228 val exuParameters = coreParams.exuParameters 229 val NRIntReadPorts = coreParams.NRIntReadPorts 230 val NRIntWritePorts = coreParams.NRIntWritePorts 231 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 232 val NRFpReadPorts = coreParams.NRFpReadPorts 233 val NRFpWritePorts = coreParams.NRFpWritePorts 234 val LoadPipelineWidth = coreParams.LoadPipelineWidth 235 val StorePipelineWidth = coreParams.StorePipelineWidth 236 val StoreBufferSize = coreParams.StoreBufferSize 237 val StoreBufferThreshold = coreParams.StoreBufferThreshold 238 val RefillSize = coreParams.RefillSize 239 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 240 val TlbEntrySize = coreParams.TlbEntrySize 241 val TlbSPEntrySize = coreParams.TlbSPEntrySize 242 val PtwL3EntrySize = coreParams.PtwL3EntrySize 243 val PtwSPEntrySize = coreParams.PtwSPEntrySize 244 val PtwL1EntrySize = coreParams.PtwL1EntrySize 245 val PtwL2EntrySize = coreParams.PtwL2EntrySize 246 val PtwMissQueueSize = coreParams.PtwMissQueueSize 247 val NumPerfCounters = coreParams.NumPerfCounters 248 249 val instBytes = if (HasCExtension) 2 else 4 250 val instOffsetBits = log2Ceil(instBytes) 251 252 val icacheParameters = coreParams.icacheParameters 253 val l1plusCacheParameters = coreParams.l1plusCacheParameters 254 val dcacheParameters = coreParams.dcacheParameters 255 256 val LRSCCycles = 100 257 258 259 // cache hierarchy configurations 260 val l1BusDataWidth = 256 261 262 val useFakeDCache = coreParams.useFakeDCache 263 val useFakePTW = coreParams.useFakePTW 264 val useFakeL1plusCache = coreParams.useFakeL1plusCache 265 // L2 configurations 266 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 267 val L1BusWidth = 256 268 val L2Size = coreParams.L2Size 269 val L2BlockSize = 64 270 val L2NWays = coreParams.L2NWays 271 val L2NSets = L2Size / L2BlockSize / L2NWays 272 273 // L3 configurations 274 val L2BusWidth = 256 275 276 // icache prefetcher 277 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 278 enable = true, 279 _type = "stream", 280 streamParams = StreamPrefetchParameters( 281 streamCnt = 2, 282 streamSize = 4, 283 ageWidth = 4, 284 blockBytes = l1plusCacheParameters.blockBytes, 285 reallocStreamOnMissInstantly = true, 286 cacheName = "icache" 287 ) 288 ) 289 290 // dcache prefetcher 291 val l2PrefetcherParameters = L2PrefetcherParameters( 292 enable = true, 293 _type = "bop", // "stream" or "bop" 294 streamParams = StreamPrefetchParameters( 295 streamCnt = 4, 296 streamSize = 4, 297 ageWidth = 4, 298 blockBytes = L2BlockSize, 299 reallocStreamOnMissInstantly = true, 300 cacheName = "dcache" 301 ), 302 bopParams = BOPParameters( 303 rrTableEntries = 256, 304 rrTagBits = 12, 305 scoreBits = 5, 306 roundMax = 50, 307 badScore = 1, 308 blockBytes = L2BlockSize, 309 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 310 ), 311 ) 312 313 // load violation predict 314 val ResetTimeMax2Pow = 20 //1078576 315 val ResetTimeMin2Pow = 10 //1024 316 // wait table parameters 317 val WaitTableSize = 1024 318 val MemPredPCWidth = log2Up(WaitTableSize) 319 val LWTUse2BitCounter = true 320 // store set parameters 321 val SSITSize = WaitTableSize 322 val LFSTSize = 32 323 val SSIDWidth = log2Up(LFSTSize) 324 val LFSTWidth = 4 325 val StoreSetEnable = true // LWT will be disabled if SS is enabled 326 327 val loadExuConfigs = coreParams.loadExuConfigs 328 val storeExuConfigs = coreParams.storeExuConfigs 329 330 val intExuConfigs = coreParams.intExuConfigs 331 332 val fpExuConfigs = coreParams.fpExuConfigs 333 334 val exuConfigs = coreParams.exuConfigs 335 336} 337