1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package device 18 19import chisel3._ 20import chisel3.util._ 21import chipsalliance.rocketchip.config.Parameters 22import freechips.rocketchip.diplomacy.AddressSet 23import utils._ 24 25class UARTIO extends Bundle { 26 val out = new Bundle { 27 val valid = Output(Bool()) 28 val ch = Output(UInt(8.W)) 29 } 30 val in = new Bundle { 31 val valid = Output(Bool()) 32 val ch = Input(UInt(8.W)) 33 } 34} 35 36class AXI4UART 37( 38 address: Seq[AddressSet] 39)(implicit p: Parameters) 40 extends AXI4SlaveModule(address, executable = false, _extra = new UARTIO) 41{ 42 override lazy val module = new AXI4SlaveModuleImp[UARTIO](this){ 43 val rxfifo = RegInit(0.U(32.W)) 44 val txfifo = Reg(UInt(32.W)) 45 val stat = RegInit(1.U(32.W)) 46 val ctrl = RegInit(0.U(32.W)) 47 48 io.extra.get.out.valid := (waddr(3,0) === 4.U && in.w.fire()) 49 io.extra.get.out.ch := in.w.bits.data(7,0) 50 io.extra.get.in.valid := (raddr(3,0) === 0.U && in.r.fire()) 51 52 val mapping = Map( 53 RegMap(0x0, io.extra.get.in.ch, RegMap.Unwritable), 54 RegMap(0x4, txfifo), 55 RegMap(0x8, stat), 56 RegMap(0xc, ctrl) 57 ) 58 59 RegMap.generate(mapping, raddr(3,0), in.r.bits.data, 60 waddr(3,0), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb >> waddr(2,0)) 61 ) 62 } 63} 64