1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import xiangshan.frontend._ 35import xiangshan.frontend.icache.ICacheParameters 36 37import freechips.rocketchip.diplomacy.AddressSet 38import system.SoCParamsKey 39import huancun._ 40import huancun.debug._ 41import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 42 43import scala.math.min 44 45case object XSTileKey extends Field[Seq[XSCoreParameters]] 46 47case object XSCoreParamsKey extends Field[XSCoreParameters] 48 49case class XSCoreParameters 50( 51 HasPrefetch: Boolean = false, 52 HartId: Int = 0, 53 XLEN: Int = 64, 54 VLEN: Int = 128, 55 ELEN: Int = 64, 56 HasMExtension: Boolean = true, 57 HasCExtension: Boolean = true, 58 HasDiv: Boolean = true, 59 HasICache: Boolean = true, 60 HasDCache: Boolean = true, 61 AddrBits: Int = 64, 62 VAddrBits: Int = 39, 63 HasFPU: Boolean = true, 64 HasVPU: Boolean = true, 65 HasCustomCSRCacheOp: Boolean = true, 66 FetchWidth: Int = 8, 67 AsidLength: Int = 16, 68 EnableBPU: Boolean = true, 69 EnableBPD: Boolean = true, 70 EnableRAS: Boolean = true, 71 EnableLB: Boolean = false, 72 EnableLoop: Boolean = true, 73 EnableSC: Boolean = true, 74 EnbaleTlbDebug: Boolean = false, 75 EnableJal: Boolean = false, 76 EnableFauFTB: Boolean = true, 77 UbtbGHRLength: Int = 4, 78 // HistoryLength: Int = 512, 79 EnableGHistDiff: Boolean = true, 80 UbtbSize: Int = 256, 81 FtbSize: Int = 2048, 82 RasSize: Int = 32, 83 CacheLineSize: Int = 512, 84 FtbWays: Int = 4, 85 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 86 // Sets Hist Tag 87 // Seq(( 2048, 2, 8), 88 // ( 2048, 9, 8), 89 // ( 2048, 13, 8), 90 // ( 2048, 20, 8), 91 // ( 2048, 26, 8), 92 // ( 2048, 44, 8), 93 // ( 2048, 73, 8), 94 // ( 2048, 256, 8)), 95 Seq(( 4096, 8, 8), 96 ( 4096, 13, 8), 97 ( 4096, 32, 8), 98 ( 4096, 119, 8)), 99 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 100 // Sets Hist Tag 101 Seq(( 256, 4, 9), 102 ( 256, 8, 9), 103 ( 512, 13, 9), 104 ( 512, 16, 9), 105 ( 512, 32, 9)), 106 SCNRows: Int = 512, 107 SCNTables: Int = 4, 108 SCCtrBits: Int = 6, 109 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 110 numBr: Int = 2, 111 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 112 ((resp_in: BranchPredictionResp, p: Parameters) => { 113 val ftb = Module(new FTB()(p)) 114 val ubtb =Module(new FauFTB()(p)) 115 // val bim = Module(new BIM()(p)) 116 val tage = Module(new Tage_SC()(p)) 117 val ras = Module(new RAS()(p)) 118 val ittage = Module(new ITTage()(p)) 119 val preds = Seq(ubtb, tage, ftb, ittage, ras) 120 preds.map(_.io := DontCare) 121 122 // ubtb.io.resp_in(0) := resp_in 123 // bim.io.resp_in(0) := ubtb.io.resp 124 // btb.io.resp_in(0) := bim.io.resp 125 // tage.io.resp_in(0) := btb.io.resp 126 // loop.io.resp_in(0) := tage.io.resp 127 ubtb.io.in.bits.resp_in(0) := resp_in 128 tage.io.in.bits.resp_in(0) := ubtb.io.out 129 ftb.io.in.bits.resp_in(0) := tage.io.out 130 ittage.io.in.bits.resp_in(0) := ftb.io.out 131 ras.io.in.bits.resp_in(0) := ittage.io.out 132 133 (preds, ras.io.out) 134 }), 135 IBufSize: Int = 48, 136 DecodeWidth: Int = 6, 137 RenameWidth: Int = 6, 138 CommitWidth: Int = 6, 139 MaxUopSize: Int = 65, 140 FtqSize: Int = 64, 141 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 142 IntLogicRegs: Int = 32, 143 FpLogicRegs: Int = 33, 144 VecLogicRegs: Int = 32 + 8 + 1, // 8: tmp, 1: vconfig 145 VCONFIG_IDX: Int = 40, 146 NRPhyRegs: Int = 192, 147 IntPhyRegs: Int = 192, 148 VfPhyRegs: Int = 192, 149 LoadQueueSize: Int = 80, 150 LoadQueueNWriteBanks: Int = 8, 151 StoreQueueSize: Int = 64, 152 StoreQueueNWriteBanks: Int = 8, 153 VlsQueueSize: Int = 8, 154 RobSize: Int = 256, 155 RabSize: Int = 256, 156 dpParams: DispatchParameters = DispatchParameters( 157 IntDqSize = 16, 158 FpDqSize = 16, 159 LsDqSize = 16, 160 IntDqDeqWidth = 6, 161 FpDqDeqWidth = 6, 162 LsDqDeqWidth = 6, 163 ), 164 intPreg: PregParams = IntPregParams( 165 numEntries = 64, 166 numRead = 14, 167 numWrite = 8, 168 ), 169 vfPreg: VfPregParams = VfPregParams( 170 numEntries = 64, 171 numRead = 14, 172 numWrite = 8, 173 ), 174 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 175 LoadPipelineWidth: Int = 2, 176 StorePipelineWidth: Int = 2, 177 VecMemSrcInWidth: Int = 2, 178 VecMemInstWbWidth: Int = 1, 179 VecMemDispatchWidth: Int = 1, 180 StoreBufferSize: Int = 16, 181 StoreBufferThreshold: Int = 7, 182 EnsbufferWidth: Int = 2, 183 UncacheBufferSize: Int = 4, 184 EnableLoadToLoadForward: Boolean = true, 185 EnableFastForward: Boolean = false, 186 EnableLdVioCheckAfterReset: Boolean = true, 187 EnableSoftPrefetchAfterReset: Boolean = true, 188 EnableCacheErrorAfterReset: Boolean = true, 189 EnableDCacheWPU: Boolean = false, 190 EnableAccurateLoadError: Boolean = true, 191 EnableUncacheWriteOutstanding: Boolean = false, 192 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 193 ReSelectLen: Int = 7, // load replay queue replay select counter len 194 itlbParameters: TLBParameters = TLBParameters( 195 name = "itlb", 196 fetchi = true, 197 useDmode = false, 198 normalNWays = 32, 199 normalReplacer = Some("plru"), 200 superNWays = 4, 201 superReplacer = Some("plru") 202 ), 203 ldtlbParameters: TLBParameters = TLBParameters( 204 name = "ldtlb", 205 normalNSets = 64, 206 normalNWays = 1, 207 normalAssociative = "sa", 208 normalReplacer = Some("setplru"), 209 superNWays = 16, 210 normalAsVictim = true, 211 outReplace = false, 212 partialStaticPMP = true, 213 outsideRecvFlush = true, 214 saveLevel = true 215 ), 216 sttlbParameters: TLBParameters = TLBParameters( 217 name = "sttlb", 218 normalNSets = 64, 219 normalNWays = 1, 220 normalAssociative = "sa", 221 normalReplacer = Some("setplru"), 222 superNWays = 16, 223 normalAsVictim = true, 224 outReplace = false, 225 partialStaticPMP = true, 226 outsideRecvFlush = true, 227 saveLevel = true 228 ), 229 pftlbParameters: TLBParameters = TLBParameters( 230 name = "pftlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 refillBothTlb: Boolean = false, 243 btlbParameters: TLBParameters = TLBParameters( 244 name = "btlb", 245 normalNSets = 1, 246 normalNWays = 64, 247 superNWays = 4, 248 ), 249 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 250 NumPerfCounters: Int = 16, 251 icacheParameters: ICacheParameters = ICacheParameters( 252 tagECC = Some("parity"), 253 dataECC = Some("parity"), 254 replacer = Some("setplru"), 255 nMissEntries = 2, 256 nProbeEntries = 2, 257 nPrefetchEntries = 2, 258 hasPrefetch = true, 259 ), 260 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 261 tagECC = Some("secded"), 262 dataECC = Some("secded"), 263 replacer = Some("setplru"), 264 nMissEntries = 16, 265 nProbeEntries = 8, 266 nReleaseEntries = 18 267 )), 268 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 269 name = "l2", 270 level = 2, 271 ways = 8, 272 sets = 1024, // default 512KB L2 273 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 274 )), 275 L2NBanks: Int = 1, 276 usePTWRepeater: Boolean = false, 277 softTLB: Boolean = false, // dpi-c l1tlb debug only 278 softPTW: Boolean = false, // dpi-c l2tlb debug only 279 softPTWDelay: Int = 1 280){ 281 def vlWidth = log2Up(VLEN) + 1 282 283 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 284 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 285 286 def intSchdParams = { 287 implicit val schdType: SchedulerType = IntScheduler() 288 val pregBits = intPreg.addrWidth 289 val numRfRead = intPreg.numRead 290 val numRfWrite = intPreg.numWrite 291 SchdBlockParams(Seq( 292 IssueBlockParams(Seq( 293 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 294 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 295 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 296 IssueBlockParams(Seq( 297 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 298 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 299 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 300 IssueBlockParams(Seq( 301 ExeUnitParams(Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 302 ExeUnitParams(Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(4, 1)))), 303 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 304 IssueBlockParams(Seq( 305 ExeUnitParams(Seq(I2fCfg, VSetRiWiCfg, VSetRiWvfCfg), Seq(VecWB(port = 6, Int.MaxValue), IntWB(port = 7, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 306 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 307 ), 308 numPregs = intPreg.numEntries, 309 numRfReadWrite = Some((numRfRead, numRfWrite)), 310 numDeqOutside = 0, 311 schdType = schdType, 312 rfDataWidth = intPreg.dataCfg.dataWidth, 313 numUopIn = dpParams.IntDqDeqWidth, 314 ) 315 } 316 def vfSchdParams = { 317 implicit val schdType: SchedulerType = VfScheduler() 318 val pregBits = vfPreg.addrWidth 319 val numRfRead = vfPreg.numRead 320 val numRfWrite = vfPreg.numWrite 321 SchdBlockParams(Seq( 322 IssueBlockParams(Seq( 323 ExeUnitParams(Seq(VialuCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 324 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 325 IssueBlockParams(Seq( 326 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 327 ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetRvfWvfCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 328 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 329 ), 330 numPregs = vfPreg.numEntries, 331 numRfReadWrite = Some((numRfRead, numRfWrite)), 332 numDeqOutside = 0, 333 schdType = schdType, 334 rfDataWidth = vfPreg.dataCfg.dataWidth, 335 numUopIn = dpParams.FpDqDeqWidth, 336 ) 337 } 338 def memSchdParams = { 339 implicit val schdType: SchedulerType = MemScheduler() 340 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 341 val rfDataWidth = 64 342 343 SchdBlockParams(Seq( 344 IssueBlockParams(Seq( 345 ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VecWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 346 ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VecWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 347 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 348 IssueBlockParams(Seq( 349 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))), 350 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(11, 0)))), 351 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 352 IssueBlockParams(Seq( 353 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 354 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 355 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 356 ), 357 numPregs = intPreg.numEntries max vfPreg.numEntries, 358 numRfReadWrite = None, 359 numDeqOutside = 0, 360 schdType = schdType, 361 rfDataWidth = rfDataWidth, 362 numUopIn = dpParams.LsDqDeqWidth, 363 ) 364 } 365 366 def backendParams: BackendParams = backend.BackendParams(Map( 367 IntScheduler() -> intSchdParams, 368 VfScheduler() -> vfSchdParams, 369 MemScheduler() -> memSchdParams, 370 ), Seq( 371 intPreg, 372 vfPreg, 373 )) 374} 375 376case object DebugOptionsKey extends Field[DebugOptions] 377 378case class DebugOptions 379( 380 FPGAPlatform: Boolean = false, 381 EnableDifftest: Boolean = false, 382 AlwaysBasicDiff: Boolean = true, 383 EnableDebug: Boolean = false, 384 EnablePerfDebug: Boolean = true, 385 UseDRAMSim: Boolean = false, 386 EnableTopDown: Boolean = false 387) 388 389trait HasXSParameter { 390 391 implicit val p: Parameters 392 393 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 394 395 val coreParams = p(XSCoreParamsKey) 396 val env = p(DebugOptionsKey) 397 398 val XLEN = coreParams.XLEN 399 val VLEN = coreParams.VLEN 400 val ELEN = coreParams.ELEN 401 val minFLen = 32 402 val fLen = 64 403 def xLen = XLEN 404 405 val HasMExtension = coreParams.HasMExtension 406 val HasCExtension = coreParams.HasCExtension 407 val HasDiv = coreParams.HasDiv 408 val HasIcache = coreParams.HasICache 409 val HasDcache = coreParams.HasDCache 410 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 411 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 412 val AsidLength = coreParams.AsidLength 413 val ReSelectLen = coreParams.ReSelectLen 414 val AddrBytes = AddrBits / 8 // unused 415 val DataBits = XLEN 416 val DataBytes = DataBits / 8 417 val HasFPU = coreParams.HasFPU 418 val HasVPU = coreParams.HasVPU 419 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 420 val FetchWidth = coreParams.FetchWidth 421 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 422 val EnableBPU = coreParams.EnableBPU 423 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 424 val EnableRAS = coreParams.EnableRAS 425 val EnableLB = coreParams.EnableLB 426 val EnableLoop = coreParams.EnableLoop 427 val EnableSC = coreParams.EnableSC 428 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 429 val HistoryLength = coreParams.HistoryLength 430 val EnableGHistDiff = coreParams.EnableGHistDiff 431 val UbtbGHRLength = coreParams.UbtbGHRLength 432 val UbtbSize = coreParams.UbtbSize 433 val EnableFauFTB = coreParams.EnableFauFTB 434 val FtbSize = coreParams.FtbSize 435 val FtbWays = coreParams.FtbWays 436 val RasSize = coreParams.RasSize 437 438 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 439 coreParams.branchPredictor(resp_in, p) 440 } 441 val numBr = coreParams.numBr 442 val TageTableInfos = coreParams.TageTableInfos 443 val TageBanks = coreParams.numBr 444 val SCNRows = coreParams.SCNRows 445 val SCCtrBits = coreParams.SCCtrBits 446 val SCHistLens = coreParams.SCHistLens 447 val SCNTables = coreParams.SCNTables 448 449 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 450 case ((n, cb), h) => (n, cb, h) 451 } 452 val ITTageTableInfos = coreParams.ITTageTableInfos 453 type FoldedHistoryInfo = Tuple2[Int, Int] 454 val foldedGHistInfos = 455 (TageTableInfos.map{ case (nRows, h, t) => 456 if (h > 0) 457 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 458 else 459 Set[FoldedHistoryInfo]() 460 }.reduce(_++_).toSet ++ 461 SCTableInfos.map{ case (nRows, _, h) => 462 if (h > 0) 463 Set((h, min(log2Ceil(nRows/TageBanks), h))) 464 else 465 Set[FoldedHistoryInfo]() 466 }.reduce(_++_).toSet ++ 467 ITTageTableInfos.map{ case (nRows, h, t) => 468 if (h > 0) 469 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 470 else 471 Set[FoldedHistoryInfo]() 472 }.reduce(_++_) ++ 473 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 474 ).toList 475 476 477 478 val CacheLineSize = coreParams.CacheLineSize 479 val CacheLineHalfWord = CacheLineSize / 16 480 val ExtHistoryLength = HistoryLength + 64 481 val IBufSize = coreParams.IBufSize 482 val DecodeWidth = coreParams.DecodeWidth 483 val RenameWidth = coreParams.RenameWidth 484 val CommitWidth = coreParams.CommitWidth 485 val MaxUopSize = coreParams.MaxUopSize 486 val FtqSize = coreParams.FtqSize 487 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 488 val IntLogicRegs = coreParams.IntLogicRegs 489 val FpLogicRegs = coreParams.FpLogicRegs 490 val VecLogicRegs = coreParams.VecLogicRegs 491 val VCONFIG_IDX = coreParams.VCONFIG_IDX 492 val NRPhyRegs = coreParams.NRPhyRegs 493 val PhyRegIdxWidth = log2Up(NRPhyRegs) 494 val IntPhyRegs = coreParams.IntPhyRegs 495 val VfPhyRegs = coreParams.VfPhyRegs 496 val IntPregIdxWidth = log2Up(IntPhyRegs) 497 val VfPregIdxWidth = log2Up(VfPhyRegs) 498 val RobSize = coreParams.RobSize 499 val RabSize = coreParams.RabSize 500 val IntRefCounterWidth = log2Ceil(RobSize) 501 val LoadQueueSize = coreParams.LoadQueueSize 502 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 503 val StoreQueueSize = coreParams.StoreQueueSize 504 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 505 val VlsQueueSize = coreParams.VlsQueueSize 506 val dpParams = coreParams.dpParams 507 508 def backendParams: BackendParams = coreParams.backendParams 509 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 510 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 511 val LoadPipelineWidth = coreParams.LoadPipelineWidth 512 val StorePipelineWidth = coreParams.StorePipelineWidth 513 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 514 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 515 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 516 val StoreBufferSize = coreParams.StoreBufferSize 517 val StoreBufferThreshold = coreParams.StoreBufferThreshold 518 val EnsbufferWidth = coreParams.EnsbufferWidth 519 val UncacheBufferSize = coreParams.UncacheBufferSize 520 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 521 val EnableFastForward = coreParams.EnableFastForward 522 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 523 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 524 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 525 val EnableDCacheWPU = coreParams.EnableDCacheWPU 526 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 527 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 528 val asidLen = coreParams.MMUAsidLen 529 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 530 val refillBothTlb = coreParams.refillBothTlb 531 val itlbParams = coreParams.itlbParameters 532 val ldtlbParams = coreParams.ldtlbParameters 533 val sttlbParams = coreParams.sttlbParameters 534 val pftlbParams = coreParams.pftlbParameters 535 val btlbParams = coreParams.btlbParameters 536 val l2tlbParams = coreParams.l2tlbParameters 537 val NumPerfCounters = coreParams.NumPerfCounters 538 539 val instBytes = if (HasCExtension) 2 else 4 540 val instOffsetBits = log2Ceil(instBytes) 541 542 val icacheParameters = coreParams.icacheParameters 543 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 544 545 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 546 // for constrained LR/SC loop 547 val LRSCCycles = 64 548 // for lr storm 549 val LRSCBackOff = 8 550 551 // cache hierarchy configurations 552 val l1BusDataWidth = 256 553 554 // load violation predict 555 val ResetTimeMax2Pow = 20 //1078576 556 val ResetTimeMin2Pow = 10 //1024 557 // wait table parameters 558 val WaitTableSize = 1024 559 val MemPredPCWidth = log2Up(WaitTableSize) 560 val LWTUse2BitCounter = true 561 // store set parameters 562 val SSITSize = WaitTableSize 563 val LFSTSize = 32 564 val SSIDWidth = log2Up(LFSTSize) 565 val LFSTWidth = 4 566 val StoreSetEnable = true // LWT will be disabled if SS is enabled 567 568 val PCntIncrStep: Int = 6 569 val numPCntHc: Int = 25 570 val numPCntPtw: Int = 19 571 572 val numCSRPCntFrontend = 8 573 val numCSRPCntCtrl = 8 574 val numCSRPCntLsu = 8 575 val numCSRPCntHc = 5 576} 577