xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision f320e0f01bd645f0a3045a8a740e60dd770734a9) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan._
23import xiangshan.backend.fu.fpu._
24
25trait HasFuLatency {
26  val latencyVal: Option[Int]
27}
28
29case class CertainLatency(value: Int) extends HasFuLatency {
30  override val latencyVal: Option[Int] = Some(value)
31}
32
33case class UncertainLatency() extends HasFuLatency {
34  override val latencyVal: Option[Int] = None
35}
36
37
38case class FuConfig
39(
40  fuGen: Parameters => FunctionUnit,
41  fuSel: FunctionUnit => Bool,
42  fuType: UInt,
43  numIntSrc: Int,
44  numFpSrc: Int,
45  writeIntRf: Boolean,
46  writeFpRf: Boolean,
47  hasRedirect: Boolean,
48  latency: HasFuLatency = CertainLatency(0),
49) {
50  def srcCnt: Int = math.max(numIntSrc, numFpSrc)
51}
52
53
54class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle {
55  val data = UInt(len.W)
56  val uop = new MicroOp
57}
58
59
60class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle {
61  val in = Flipped(DecoupledIO(new Bundle() {
62    val src = Vec(3, UInt(len.W))
63    val uop = new MicroOp
64  }))
65
66  val out = DecoupledIO(new FuOutput(len))
67
68  val redirectIn = Flipped(ValidIO(new Redirect))
69  val flushIn = Input(Bool())
70}
71
72abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule {
73
74  val io = IO(new FunctionUnitIO(len))
75
76}
77
78trait HasPipelineReg {
79  this: FunctionUnit =>
80
81  def latency: Int
82
83  require(latency > 0)
84
85  val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B))
86  val rdyVec = Array.fill(latency)(Wire(Bool())) :+ io.out.ready
87  val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp))
88
89
90  // if flush(0), valid 0 will not given, so set flushVec(0) to false.B
91  val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.roqIdx.needFlush(io.redirectIn, io.flushIn))
92
93  for (i <- 0 until latency) {
94    rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1)
95  }
96
97  for (i <- 1 to latency) {
98    when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){
99      validVec(i) := validVec(i - 1)
100      uopVec(i) := uopVec(i - 1)
101    }.elsewhen(flushVec(i) || rdyVec(i)){
102      validVec(i) := false.B
103    }
104  }
105
106  io.in.ready := rdyVec(0)
107  io.out.valid := validVec.last
108  io.out.bits.uop := uopVec.last
109
110  def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1)
111
112  def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable(
113    next,
114    enable = regEnable(i)
115  )
116
117  def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next)
118
119  def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next)
120
121  def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next)
122
123  def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next)
124
125  def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next)
126}
127