perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

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Backend: fix Uncertain Layency Fu's clock gate (#3085)

Functionunit: move parameterized delay for fixtiming to latency field renamed as extralatency

Merge upstream/master into tmp-backend-merge-master

Bump rocket-chip (#2353)

config: add `uncertainLatencyVal` support

backend,Core: remove dead code and comments

v2backend: huge tmp commit

chore(ExuBlock): print exuBlock/exeUnit/FU's configs message

backend: change vector relative IO to 128bits

vpu: add vipu(with adder that not works) into fmacExeUnit

fu: allow bypass from input buffer

dcache: repipeline ecc check logic for timing (#1582)

This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing.
Now ecc error is checked 1 cycle after r

dcache: repipeline ecc check logic for timing (#1582)

This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing.
Now ecc error is checked 1 cycle after reading result from data sram. An extra cycle is added for load
writeback to ROB.

Future work: move the pipeline to https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/backend/CtrlBlock.scala#L266-L277, which add a regnext.

* dcache: repipeline ecc check logic for timing

* chore: fix normal loadAccessFault logic

* wbu: delay load unit wb for 1 cycle

* dcache: add 1 extra cycle for beu error report

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fix for chipsalliance/chisel3#2496 (#1563)

core: refactor writeback parameters (#1327)

This commit adds WritebackSink and WritebackSource parameters for
multiple modules. These traits hide implementation details from
other modules by defin

core: refactor writeback parameters (#1327)

This commit adds WritebackSink and WritebackSource parameters for
multiple modules. These traits hide implementation details from
other modules by defining IO-related functions in modules.

By using WritebackSink, ROB is able to choose the writeback sources.
Now fflags and exceptions are connected from exe units to reduce write
ports and optimize timing.

Further optimizations on write-back to RS and better coding style to
be added later.

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core: use redirect ports for flush (#1121)

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

backend: clean up exception vector usages (#1026)

This commit cleans up exception vector usages in backend.

Previously the exception vector will go through the pipeline with the
uop. However, in

backend: clean up exception vector usages (#1026)

This commit cleans up exception vector usages in backend.

Previously the exception vector will go through the pipeline with the
uop. However, instructions with exceptions will enter ROB when they are
dispatched. Thus, actually we don't need the exception vector when an
instruction enters a function unit.

* exceptionVec, flushPipe, replayInst are reset when an instruction
enters function units.

* For execution units that don't have exceptions, we reset their output
exception vectors to avoid ROB to record them.

* Move replayInst to CtrlSignals.

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backend,fu: add InputBuffer for fdivSqrt (#990)

This commit adds an 8-entry buffer for fdivSqrt function unit input.
Set hasInputBuffer to true to enable input buffers for other function
units.

backend, fu: support fastUopOut for pipelined fu (#966)

This commit adds fastUopOut support for pipelined function units via
implementing fastUopOut in trait HasPipelineReg.

The following functi

backend, fu: support fastUopOut for pipelined fu (#966)

This commit adds fastUopOut support for pipelined function units via
implementing fastUopOut in trait HasPipelineReg.

The following function units now support fastUopOut:
- MUL
- FMA
- F2I
- F2F

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backend,fu: allow early arbitration via fastUopOut (#962)

This commit adds a fastUopOut option to function units. This allows the
function units to give valid and uop one cycle before its output da

backend,fu: allow early arbitration via fastUopOut (#962)

This commit adds a fastUopOut option to function units. This allows the
function units to give valid and uop one cycle before its output data is
ready. FastUopOut lets writeback arbitration happen one cycle before
data is ready and helps optimize the timing.

Since some function units are not ready for this new feature, this
commit adds a fastImplemented option to allow function units to have
fastUopOut but the data is still at the same cycle as uop. This option
will delay the data for one cycle and may cause performance degradation.
FastImplemented should be true after function units support fastUopOut.

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l2, core: add more performance counters (#942)

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters

l2, core: add more performance counters (#942)

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters in bus pmu

* Insert BusPMU between L3 and L2

* add some TMA perfcnt



Co-authored-by: LinJiawei <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: wangkaifan <[email protected]>

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exu: add suggestName to function units (#944)

backend: add ExuBlock to wrap execution units and RS (#903)

Backend --> ExuBlock --> FuBlock --> Exu --> Function Units
--> --> Scheduler --> RS

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.