xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision 1a0f06ee6669d8d336929ef6728eceb5b9e125d5) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan._
23import xiangshan.backend.fu.fpu._
24
25trait HasFuLatency {
26  val latencyVal: Option[Int]
27}
28
29case class CertainLatency(value: Int) extends HasFuLatency {
30  override val latencyVal: Option[Int] = Some(value)
31}
32
33case class UncertainLatency() extends HasFuLatency {
34  override val latencyVal: Option[Int] = None
35}
36
37
38case class FuConfig
39(
40  name: String,
41  fuGen: Parameters => FunctionUnit,
42  fuSel: FunctionUnit => Bool,
43  fuType: UInt,
44  numIntSrc: Int,
45  numFpSrc: Int,
46  writeIntRf: Boolean,
47  writeFpRf: Boolean,
48  hasRedirect: Boolean,
49  latency: HasFuLatency = CertainLatency(0),
50) {
51  def srcCnt: Int = math.max(numIntSrc, numFpSrc)
52}
53
54
55class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle {
56  val data = UInt(len.W)
57  val uop = new MicroOp
58}
59
60
61class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle {
62  val in = Flipped(DecoupledIO(new Bundle() {
63    val src = Vec(3, UInt(len.W))
64    val uop = new MicroOp
65  }))
66
67  val out = DecoupledIO(new FuOutput(len))
68
69  val redirectIn = Flipped(ValidIO(new Redirect))
70  val flushIn = Input(Bool())
71}
72
73abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule {
74
75  val io = IO(new FunctionUnitIO(len))
76
77}
78
79abstract class FUWithRedirect(len: Int = 64)(implicit p: Parameters) extends FunctionUnit(len: Int) with HasRedirectOut
80
81trait HasPipelineReg {
82  this: FunctionUnit =>
83
84  def latency: Int
85
86  require(latency > 0)
87
88  val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B))
89  val rdyVec = Array.fill(latency)(Wire(Bool())) :+ io.out.ready
90  val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp))
91
92
93  // if flush(0), valid 0 will not given, so set flushVec(0) to false.B
94  val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.roqIdx.needFlush(io.redirectIn, io.flushIn))
95
96  for (i <- 0 until latency) {
97    rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1)
98  }
99
100  for (i <- 1 to latency) {
101    when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){
102      validVec(i) := validVec(i - 1)
103      uopVec(i) := uopVec(i - 1)
104    }.elsewhen(flushVec(i) || rdyVec(i)){
105      validVec(i) := false.B
106    }
107  }
108
109  io.in.ready := rdyVec(0)
110  io.out.valid := validVec.last
111  io.out.bits.uop := uopVec.last
112
113  def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1)
114
115  def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable(
116    next,
117    enable = regEnable(i)
118  )
119
120  def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next)
121
122  def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next)
123
124  def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next)
125
126  def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next)
127
128  def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next)
129}
130