1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils.XSPerfAccumulate 23import xiangshan._ 24import xiangshan.backend.fu.fpu._ 25 26trait HasFuLatency { 27 val latencyVal: Option[Int] 28} 29 30case class CertainLatency(value: Int) extends HasFuLatency { 31 override val latencyVal: Option[Int] = Some(value) 32} 33 34case class UncertainLatency() extends HasFuLatency { 35 override val latencyVal: Option[Int] = None 36} 37 38 39case class FuConfig 40( 41 name: String, 42 fuGen: Parameters => FunctionUnit, 43 fuSel: MicroOp => Bool, 44 fuType: UInt, 45 numIntSrc: Int, 46 numFpSrc: Int, 47 numVecSrc: Int = 0, 48 writeIntRf: Boolean, 49 writeFpRf: Boolean, 50 writeVecRf: Boolean = false, 51 writeFflags: Boolean = false, 52 hasRedirect: Boolean = false, 53 latency: HasFuLatency = CertainLatency(0), 54 fastUopOut: Boolean = false, 55 fastImplemented: Boolean = false, 56 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 57 exceptionOut: Seq[Int] = Seq(), 58 hasLoadError: Boolean = false, 59 flushPipe: Boolean = false, 60 replayInst: Boolean = false, 61 trigger: Boolean = false 62) { 63 def srcCnt: Int = math.max(math.max(numIntSrc, numFpSrc), numVecSrc) 64 def isVectorFU: Boolean = (numVecSrc > 0) && writeVecRf 65} 66 67 68class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle { 69 val data = UInt(len.W) 70 val uop = new MicroOp 71} 72 73class FunctionUnitInput(val len: Int)(implicit p: Parameters) extends XSBundle { 74 val src = Vec(3, UInt(len.W)) 75 val uop = new MicroOp 76} 77 78class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle { 79 val in = Flipped(DecoupledIO(new FunctionUnitInput(len))) 80 81 val out = DecoupledIO(new FuOutput(len)) 82 83 val redirectIn = Flipped(ValidIO(new Redirect)) 84} 85 86abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule { 87 88 val io = IO(new FunctionUnitIO(len)) 89 90 XSPerfAccumulate("in_valid", io.in.valid) 91 XSPerfAccumulate("in_fire", io.in.fire) 92 XSPerfAccumulate("out_valid", io.out.valid) 93 XSPerfAccumulate("out_fire", io.out.fire) 94 95} 96 97abstract class FUWithRedirect(len: Int = 64)(implicit p: Parameters) extends FunctionUnit(len: Int) with HasRedirectOut 98 99trait HasPipelineReg { 100 this: FunctionUnit => 101 102 def latency: Int 103 104 require(latency > 0) 105 106 val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B)) 107 val rdyVec = (Array.fill(latency - 1)(Wire(Bool())) :+ io.out.ready) :+ WireInit(true.B) 108 val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp)) 109 110 111 // if flush(0), valid 0 will not given, so set flushVec(0) to false.B 112 val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.robIdx.needFlush(io.redirectIn)) 113 114 for (i <- 0 until latency - 1) { 115 rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1) 116 } 117 118 for (i <- 1 to latency) { 119 when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){ 120 validVec(i) := validVec(i - 1) 121 uopVec(i) := uopVec(i - 1) 122 }.elsewhen(flushVec(i) || rdyVec(i)){ 123 validVec(i) := false.B 124 } 125 } 126 127 io.in.ready := rdyVec(0) 128 io.out.valid := validVec.takeRight(2).head 129 io.out.bits.uop := uopVec.takeRight(2).head 130 131 def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1) 132 133 def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable( 134 next, 135 regEnable(i) 136 ) 137 138 def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next) 139 140 def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next) 141 142 def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next) 143 144 def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next) 145 146 def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next) 147} 148