1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils.XSPerfAccumulate 23import xiangshan._ 24import xiangshan.backend.fu.fpu._ 25 26trait HasFuLatency { 27 val latencyVal: Option[Int] 28} 29 30case class CertainLatency(value: Int) extends HasFuLatency { 31 override val latencyVal: Option[Int] = Some(value) 32} 33 34case class UncertainLatency() extends HasFuLatency { 35 override val latencyVal: Option[Int] = None 36} 37 38 39case class FuConfig 40( 41 name: String, 42 fuGen: Parameters => FunctionUnit, 43 fuSel: MicroOp => Bool, 44 fuType: UInt, 45 numIntSrc: Int, 46 numFpSrc: Int, 47 writeIntRf: Boolean, 48 writeFpRf: Boolean, 49 writeFflags: Boolean = false, 50 hasRedirect: Boolean = false, 51 latency: HasFuLatency = CertainLatency(0), 52 fastUopOut: Boolean = false, 53 fastImplemented: Boolean = false, 54 hasInputBuffer: Boolean = false, 55 exceptionOut: Seq[Int] = Seq(), 56 flushPipe: Boolean = false, 57 replayInst: Boolean = false, 58 trigger: Boolean = false 59) { 60 def srcCnt: Int = math.max(numIntSrc, numFpSrc) 61} 62 63 64class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle { 65 val data = UInt(len.W) 66 val uop = new MicroOp 67} 68 69class FunctionUnitInput(val len: Int)(implicit p: Parameters) extends XSBundle { 70 val src = Vec(3, UInt(len.W)) 71 val uop = new MicroOp 72} 73 74class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle { 75 val in = Flipped(DecoupledIO(new FunctionUnitInput(len))) 76 77 val out = DecoupledIO(new FuOutput(len)) 78 79 val redirectIn = Flipped(ValidIO(new Redirect)) 80} 81 82abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule { 83 84 val io = IO(new FunctionUnitIO(len)) 85 86 XSPerfAccumulate("in_valid", io.in.valid) 87 XSPerfAccumulate("in_fire", io.in.fire) 88 XSPerfAccumulate("out_valid", io.out.valid) 89 XSPerfAccumulate("out_fire", io.out.fire) 90 91} 92 93abstract class FUWithRedirect(len: Int = 64)(implicit p: Parameters) extends FunctionUnit(len: Int) with HasRedirectOut 94 95trait HasPipelineReg { 96 this: FunctionUnit => 97 98 def latency: Int 99 100 require(latency > 0) 101 102 val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B)) 103 val rdyVec = (Array.fill(latency - 1)(Wire(Bool())) :+ io.out.ready) :+ WireInit(true.B) 104 val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp)) 105 106 107 // if flush(0), valid 0 will not given, so set flushVec(0) to false.B 108 val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.robIdx.needFlush(io.redirectIn)) 109 110 for (i <- 0 until latency - 1) { 111 rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1) 112 } 113 114 for (i <- 1 to latency) { 115 when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){ 116 validVec(i) := validVec(i - 1) 117 uopVec(i) := uopVec(i - 1) 118 }.elsewhen(flushVec(i) || rdyVec(i)){ 119 validVec(i) := false.B 120 } 121 } 122 123 io.in.ready := rdyVec(0) 124 io.out.valid := validVec.takeRight(2).head 125 io.out.bits.uop := uopVec.takeRight(2).head 126 127 def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1) 128 129 def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable( 130 next, 131 enable = regEnable(i) 132 ) 133 134 def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next) 135 136 def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next) 137 138 def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next) 139 140 def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next) 141 142 def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next) 143} 144