xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision c88c3a2ad8d5caddcf38e659cf944c9bb09bb6ad) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils.XSPerfAccumulate
23import xiangshan._
24import xiangshan.backend.fu.fpu._
25
26trait HasFuLatency {
27  val latencyVal: Option[Int]
28}
29
30case class CertainLatency(value: Int) extends HasFuLatency {
31  override val latencyVal: Option[Int] = Some(value)
32}
33
34case class UncertainLatency() extends HasFuLatency {
35  override val latencyVal: Option[Int] = None
36}
37
38
39case class FuConfig
40(
41  name: String,
42  fuGen: Parameters => FunctionUnit,
43  fuSel: MicroOp => Bool,
44  fuType: UInt,
45  numIntSrc: Int,
46  numFpSrc: Int,
47  writeIntRf: Boolean,
48  writeFpRf: Boolean,
49  hasRedirect: Boolean,
50  latency: HasFuLatency = CertainLatency(0),
51  fastUopOut: Boolean = false,
52  fastImplemented: Boolean = false,
53  hasInputBuffer: Boolean = false,
54  hasExceptionOut: Boolean = false
55) {
56  def srcCnt: Int = math.max(numIntSrc, numFpSrc)
57}
58
59
60class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle {
61  val data = UInt(len.W)
62  val uop = new MicroOp
63}
64
65class FunctionUnitInput(val len: Int)(implicit p: Parameters) extends XSBundle {
66  val src = Vec(3, UInt(len.W))
67  val uop = new MicroOp
68}
69
70class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle {
71  val in = Flipped(DecoupledIO(new FunctionUnitInput(len)))
72
73  val out = DecoupledIO(new FuOutput(len))
74
75  val redirectIn = Flipped(ValidIO(new Redirect))
76  val flushIn = Input(Bool())
77}
78
79abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule {
80
81  val io = IO(new FunctionUnitIO(len))
82
83  XSPerfAccumulate("in_valid", io.in.valid)
84  XSPerfAccumulate("in_fire", io.in.fire)
85  XSPerfAccumulate("out_valid", io.out.valid)
86  XSPerfAccumulate("out_fire", io.out.fire)
87
88}
89
90abstract class FUWithRedirect(len: Int = 64)(implicit p: Parameters) extends FunctionUnit(len: Int) with HasRedirectOut
91
92trait HasPipelineReg {
93  this: FunctionUnit =>
94
95  def latency: Int
96
97  require(latency > 0)
98
99  val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B))
100  val rdyVec = (Array.fill(latency - 1)(Wire(Bool())) :+ io.out.ready) :+ WireInit(true.B)
101  val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp))
102
103
104  // if flush(0), valid 0 will not given, so set flushVec(0) to false.B
105  val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.roqIdx.needFlush(io.redirectIn, io.flushIn))
106
107  for (i <- 0 until latency - 1) {
108    rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1)
109  }
110
111  for (i <- 1 to latency) {
112    when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){
113      validVec(i) := validVec(i - 1)
114      uopVec(i) := uopVec(i - 1)
115    }.elsewhen(flushVec(i) || rdyVec(i)){
116      validVec(i) := false.B
117    }
118  }
119
120  io.in.ready := rdyVec(0)
121  io.out.valid := validVec.takeRight(2).head
122  io.out.bits.uop := uopVec.takeRight(2).head
123
124  def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1)
125
126  def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable(
127    next,
128    enable = regEnable(i)
129  )
130
131  def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next)
132
133  def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next)
134
135  def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next)
136
137  def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next)
138
139  def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next)
140}
141