xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision 5ee7cabe33e2ee2c1243e4934ff47c80b7b7064d)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils.XSPerfAccumulate
23import xiangshan._
24import xiangshan.backend.fu.fpu._
25
26trait HasFuLatency {
27  val latencyVal: Option[Int]
28}
29
30case class CertainLatency(value: Int) extends HasFuLatency {
31  override val latencyVal: Option[Int] = Some(value)
32}
33
34case class UncertainLatency() extends HasFuLatency {
35  override val latencyVal: Option[Int] = None
36}
37
38
39case class FuConfig
40(
41  name: String,
42  fuGen: Parameters => FunctionUnit,
43  fuSel: MicroOp => Bool,
44  fuType: UInt,
45  numIntSrc: Int,
46  numFpSrc: Int,
47  writeIntRf: Boolean,
48  writeFpRf: Boolean,
49  writeFflags: Boolean = false,
50  hasRedirect: Boolean = false,
51  latency: HasFuLatency = CertainLatency(0),
52  fastUopOut: Boolean = false,
53  fastImplemented: Boolean = false,
54  hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false),
55  exceptionOut: Seq[Int] = Seq(),
56  hasLoadError: Boolean = false,
57  flushPipe: Boolean = false,
58  replayInst: Boolean = false,
59  trigger: Boolean = false
60) {
61  def srcCnt: Int = math.max(numIntSrc, numFpSrc)
62}
63
64
65class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle {
66  val data = UInt(len.W)
67  val uop = new MicroOp
68}
69
70class FunctionUnitInput(val len: Int)(implicit p: Parameters) extends XSBundle {
71  val src = Vec(3, UInt(len.W))
72  val uop = new MicroOp
73}
74
75class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle {
76  val in = Flipped(DecoupledIO(new FunctionUnitInput(len)))
77
78  val out = DecoupledIO(new FuOutput(len))
79
80  val redirectIn = Flipped(ValidIO(new Redirect))
81}
82
83abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule {
84
85  val io = IO(new FunctionUnitIO(len))
86
87  XSPerfAccumulate("in_valid", io.in.valid)
88  XSPerfAccumulate("in_fire", io.in.fire)
89  XSPerfAccumulate("out_valid", io.out.valid)
90  XSPerfAccumulate("out_fire", io.out.fire)
91
92}
93
94abstract class FUWithRedirect(len: Int = 64)(implicit p: Parameters) extends FunctionUnit(len: Int) with HasRedirectOut
95
96trait HasPipelineReg {
97  this: FunctionUnit =>
98
99  def latency: Int
100
101  require(latency > 0)
102
103  val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B))
104  val rdyVec = (Array.fill(latency - 1)(Wire(Bool())) :+ io.out.ready) :+ WireInit(true.B)
105  val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp))
106
107
108  // if flush(0), valid 0 will not given, so set flushVec(0) to false.B
109  val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.robIdx.needFlush(io.redirectIn))
110
111  for (i <- 0 until latency - 1) {
112    rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1)
113  }
114
115  for (i <- 1 to latency) {
116    when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){
117      validVec(i) := validVec(i - 1)
118      uopVec(i) := uopVec(i - 1)
119    }.elsewhen(flushVec(i) || rdyVec(i)){
120      validVec(i) := false.B
121    }
122  }
123
124  io.in.ready := rdyVec(0)
125  io.out.valid := validVec.takeRight(2).head
126  io.out.bits.uop := uopVec.takeRight(2).head
127
128  def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1)
129
130  def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable(
131    next,
132    regEnable(i)
133  )
134
135  def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next)
136
137  def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next)
138
139  def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next)
140
141  def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next)
142
143  def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next)
144}
145