xref: /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala (revision b2482bc10e275ad2ad3a09993a61648f9648d96e) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils.XSPerfAccumulate
23import xiangshan._
24import xiangshan.backend.fu.fpu._
25
26trait HasFuLatency {
27  val latencyVal: Option[Int]
28}
29
30case class CertainLatency(value: Int) extends HasFuLatency {
31  override val latencyVal: Option[Int] = Some(value)
32}
33
34case class UncertainLatency() extends HasFuLatency {
35  override val latencyVal: Option[Int] = None
36}
37
38
39case class FuConfig
40(
41  name: String,
42  fuGen: Parameters => FunctionUnit,
43  fuSel: FunctionUnit => Bool,
44  fuType: UInt,
45  numIntSrc: Int,
46  numFpSrc: Int,
47  writeIntRf: Boolean,
48  writeFpRf: Boolean,
49  hasRedirect: Boolean,
50  latency: HasFuLatency = CertainLatency(0),
51  fastUopOut: Boolean = false,
52  fastImplemented: Boolean = false
53) {
54  def srcCnt: Int = math.max(numIntSrc, numFpSrc)
55}
56
57
58class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle {
59  val data = UInt(len.W)
60  val uop = new MicroOp
61}
62
63
64class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle {
65  val in = Flipped(DecoupledIO(new Bundle() {
66    val src = Vec(3, UInt(len.W))
67    val uop = new MicroOp
68  }))
69
70  val out = DecoupledIO(new FuOutput(len))
71
72  val redirectIn = Flipped(ValidIO(new Redirect))
73  val flushIn = Input(Bool())
74}
75
76abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule {
77
78  val io = IO(new FunctionUnitIO(len))
79
80  XSPerfAccumulate("in_valid", io.in.valid)
81  XSPerfAccumulate("in_fire", io.in.fire)
82  XSPerfAccumulate("out_valid", io.out.valid)
83  XSPerfAccumulate("out_fire", io.out.fire)
84
85}
86
87abstract class FUWithRedirect(len: Int = 64)(implicit p: Parameters) extends FunctionUnit(len: Int) with HasRedirectOut
88
89trait HasPipelineReg {
90  this: FunctionUnit =>
91
92  def latency: Int
93
94  require(latency > 0)
95
96  val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B))
97  val rdyVec = (Array.fill(latency - 1)(Wire(Bool())) :+ io.out.ready) :+ WireInit(true.B)
98  val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp))
99
100
101  // if flush(0), valid 0 will not given, so set flushVec(0) to false.B
102  val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.roqIdx.needFlush(io.redirectIn, io.flushIn))
103
104  for (i <- 0 until latency - 1) {
105    rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1)
106  }
107
108  for (i <- 1 to latency) {
109    when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){
110      validVec(i) := validVec(i - 1)
111      uopVec(i) := uopVec(i - 1)
112    }.elsewhen(flushVec(i) || rdyVec(i)){
113      validVec(i) := false.B
114    }
115  }
116
117  io.in.ready := rdyVec(0)
118  io.out.valid := validVec.takeRight(2).head
119  io.out.bits.uop := uopVec.takeRight(2).head
120
121  def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1)
122
123  def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable(
124    next,
125    enable = regEnable(i)
126  )
127
128  def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next)
129
130  def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next)
131
132  def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next)
133
134  def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next)
135
136  def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next)
137}
138