1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.fu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils.XSPerfAccumulate 23import xiangshan._ 24import xiangshan.backend.fu.fpu._ 25 26trait HasFuLatency { 27 val latencyVal: Option[Int] 28} 29 30case class CertainLatency(value: Int) extends HasFuLatency { 31 override val latencyVal: Option[Int] = Some(value) 32} 33 34case class UncertainLatency() extends HasFuLatency { 35 override val latencyVal: Option[Int] = None 36} 37 38 39case class FuConfig 40( 41 name: String, 42 fuGen: Parameters => FunctionUnit, 43 fuSel: FunctionUnit => Bool, 44 fuType: UInt, 45 numIntSrc: Int, 46 numFpSrc: Int, 47 writeIntRf: Boolean, 48 writeFpRf: Boolean, 49 hasRedirect: Boolean, 50 latency: HasFuLatency = CertainLatency(0), 51) { 52 def srcCnt: Int = math.max(numIntSrc, numFpSrc) 53} 54 55 56class FuOutput(val len: Int)(implicit p: Parameters) extends XSBundle { 57 val data = UInt(len.W) 58 val uop = new MicroOp 59} 60 61 62class FunctionUnitIO(val len: Int)(implicit p: Parameters) extends XSBundle { 63 val in = Flipped(DecoupledIO(new Bundle() { 64 val src = Vec(3, UInt(len.W)) 65 val uop = new MicroOp 66 })) 67 68 val out = DecoupledIO(new FuOutput(len)) 69 70 val redirectIn = Flipped(ValidIO(new Redirect)) 71 val flushIn = Input(Bool()) 72} 73 74abstract class FunctionUnit(len: Int = 64)(implicit p: Parameters) extends XSModule { 75 76 val io = IO(new FunctionUnitIO(len)) 77 78 XSPerfAccumulate("in_valid", io.in.valid) 79 XSPerfAccumulate("in_fire", io.in.fire) 80 XSPerfAccumulate("out_valid", io.out.valid) 81 XSPerfAccumulate("out_fire", io.out.fire) 82 83} 84 85abstract class FUWithRedirect(len: Int = 64)(implicit p: Parameters) extends FunctionUnit(len: Int) with HasRedirectOut 86 87trait HasPipelineReg { 88 this: FunctionUnit => 89 90 def latency: Int 91 92 require(latency > 0) 93 94 val validVec = io.in.valid +: Array.fill(latency)(RegInit(false.B)) 95 val rdyVec = Array.fill(latency)(Wire(Bool())) :+ io.out.ready 96 val uopVec = io.in.bits.uop +: Array.fill(latency)(Reg(new MicroOp)) 97 98 99 // if flush(0), valid 0 will not given, so set flushVec(0) to false.B 100 val flushVec = validVec.zip(uopVec).map(x => x._1 && x._2.roqIdx.needFlush(io.redirectIn, io.flushIn)) 101 102 for (i <- 0 until latency) { 103 rdyVec(i) := !validVec(i + 1) || rdyVec(i + 1) 104 } 105 106 for (i <- 1 to latency) { 107 when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){ 108 validVec(i) := validVec(i - 1) 109 uopVec(i) := uopVec(i - 1) 110 }.elsewhen(flushVec(i) || rdyVec(i)){ 111 validVec(i) := false.B 112 } 113 } 114 115 io.in.ready := rdyVec(0) 116 io.out.valid := validVec.last 117 io.out.bits.uop := uopVec.last 118 119 def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1) 120 121 def PipelineReg[TT <: Data](i: Int)(next: TT) = RegEnable( 122 next, 123 enable = regEnable(i) 124 ) 125 126 def S1Reg[TT <: Data](next: TT): TT = PipelineReg[TT](1)(next) 127 128 def S2Reg[TT <: Data](next: TT): TT = PipelineReg[TT](2)(next) 129 130 def S3Reg[TT <: Data](next: TT): TT = PipelineReg[TT](3)(next) 131 132 def S4Reg[TT <: Data](next: TT): TT = PipelineReg[TT](4)(next) 133 134 def S5Reg[TT <: Data](next: TT): TT = PipelineReg[TT](5)(next) 135} 136