1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config 20import chipsalliance.rocketchip.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp} 24import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple} 25import freechips.rocketchip.tile.HasFPUParameters 26import system.HasSoCParameter 27import utility._ 28import utils._ 29import xiangshan.backend._ 30import xiangshan.backend.exu.{ExuConfig, Wb2Ctrl, WbArbiterWrapper} 31import xiangshan.cache.mmu._ 32import xiangshan.frontend._ 33import xiangshan.backend._ 34import xiangshan.mem.L1PrefetchFuzzer 35 36import scala.collection.mutable.ListBuffer 37 38abstract class XSModule(implicit val p: Parameters) extends Module 39 with HasXSParameter 40 with HasFPUParameters 41 42//remove this trait after impl module logic 43trait NeedImpl { 44 this: RawModule => 45 override protected def IO[T <: Data](iodef: T): T = { 46 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 47 val io = chisel3.experimental.IO(iodef) 48 io <> DontCare 49 io 50 } 51} 52 53abstract class XSBundle(implicit val p: Parameters) extends Bundle 54 with HasXSParameter 55 56abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule 57 with HasXSParameter 58{ 59 // interrupt sinks 60 val clint_int_sink = IntSinkNode(IntSinkPortSimple(1, 2)) 61 val debug_int_sink = IntSinkNode(IntSinkPortSimple(1, 1)) 62 val plic_int_sink = IntSinkNode(IntSinkPortSimple(2, 1)) 63 // outer facing nodes 64 val frontend = LazyModule(new Frontend()) 65 val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO())) 66 val backend = LazyModule(new Backend(backendParams)) 67 68 val memBlock = LazyModule(new MemBlock) 69} 70 71class XSCore()(implicit p: config.Parameters) extends XSCoreBase 72 with HasXSDts 73{ 74 lazy val module = new XSCoreImp(this) 75} 76 77class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer) 78 with HasXSParameter 79 with HasSoCParameter { 80 val io = IO(new Bundle { 81 val hartId = Input(UInt(64.W)) 82 val reset_vector = Input(UInt(PAddrBits.W)) 83 val cpu_halt = Output(Bool()) 84 val l2_pf_enable = Output(Bool()) 85 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks, new PerfEvent)) 86 val beu_errors = Output(new XSL1BusErrors()) 87 val l2_hint = Input(Valid(new L2ToL1Hint())) 88 }) 89 90 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 91 92 val frontend = outer.frontend.module 93 val backend = outer.backend.module 94 val memBlock = outer.memBlock.module 95 96 val fenceio = backend.io.fenceio 97 98 frontend.io.hartId := io.hartId 99 frontend.io.backend <> backend.io.frontend 100 frontend.io.sfence <> backend.io.frontendSfence 101 frontend.io.tlbCsr <> backend.io.frontendTlbCsr 102 frontend.io.csrCtrl <> backend.io.frontendCsrCtrl 103 frontend.io.fencei <> fenceio.fencei 104 105 backend.io.fromTop.hartId := io.hartId 106 backend.io.fromTop.externalInterrupt.msip := outer.clint_int_sink.in.head._1(0) 107 backend.io.fromTop.externalInterrupt.mtip := outer.clint_int_sink.in.head._1(1) 108 backend.io.fromTop.externalInterrupt.meip := outer.plic_int_sink.in.head._1(0) 109 backend.io.fromTop.externalInterrupt.seip := outer.plic_int_sink.in.last._1(0) 110 backend.io.fromTop.externalInterrupt.debug := outer.debug_int_sink.in.head._1(0) 111 112 backend.io.frontendCsrDistributedUpdate := frontend.io.csrUpdate 113 114 backend.io.mem.stIn.zip(memBlock.io.stIn).foreach { case (sink, source) => 115 sink.valid := source.valid 116 sink.bits := 0.U.asTypeOf(sink.bits) 117 sink.bits.robIdx := source.bits.uop.robIdx 118 sink.bits.ssid := source.bits.uop.ssid 119 sink.bits.storeSetHit := source.bits.uop.storeSetHit 120 // The other signals have not been used 121 } 122 backend.io.mem.memoryViolation <> memBlock.io.memoryViolation 123 backend.io.mem.lsqEnqIO <> memBlock.io.enqLsq 124 backend.io.mem.sqDeq := memBlock.io.sqDeq 125 backend.io.mem.lqDeq := memBlock.io.lqDeq 126 backend.io.mem.lqCancelCnt := memBlock.io.lqCancelCnt 127 backend.io.mem.sqCancelCnt := memBlock.io.sqCancelCnt 128 backend.io.mem.otherFastWakeup := memBlock.io.otherFastWakeup 129 backend.io.mem.ldaIqFeedback <> memBlock.io.ldaIqFeedback 130 backend.io.mem.staIqFeedback <> memBlock.io.staIqFeedback 131 backend.io.mem.writeBack.zip(memBlock.io.writeback).foreach { case(back, mem) => 132 back <> mem 133 } 134 135 frontend.io.reset_vector := io.reset_vector 136 137 io.cpu_halt := backend.io.toTop.cpuHalted 138 139 // memblock error exception writeback, 1 cycle after normal writeback 140 backend.io.mem.s3_delayed_load_error <> memBlock.io.s3_delayed_load_error 141 142 io.beu_errors.icache <> frontend.io.error.toL1BusErrorUnitInfo() 143 io.beu_errors.dcache <> memBlock.io.error.toL1BusErrorUnitInfo() 144 145 memBlock.io.hartId := io.hartId 146 memBlock.io.issue.zip(backend.io.mem.issueUops).foreach { case(memIssue, backIssue) => 147 memIssue <> backIssue 148 } 149 // By default, instructions do not have exceptions when they enter the function units. 150 memBlock.io.issue.map(_.bits.uop.clearExceptions()) 151 backend.io.mem.loadFastMatch <> memBlock.io.loadFastMatch 152 backend.io.mem.loadFastImm <> memBlock.io.loadFastImm 153 backend.io.mem.exceptionVAddr := memBlock.io.lsqio.exceptionAddr.vaddr 154 backend.io.mem.csrDistributedUpdate := memBlock.io.csrUpdate 155 156 backend.io.perf.frontendInfo := frontend.io.frontendInfo 157 backend.io.perf.memInfo := memBlock.io.memInfo 158 backend.io.perf.perfEventsFrontend := frontend.getPerf 159 backend.io.perf.perfEventsLsu := memBlock.getPerf 160 backend.io.perf.perfEventsHc := io.perfEvents 161 162 memBlock.io.sfence <> backend.io.mem.sfence 163 memBlock.io.fenceToSbuffer <> backend.io.mem.toSbuffer 164 165 memBlock.io.redirect <> backend.io.mem.redirect 166 memBlock.io.csrCtrl <> backend.io.mem.csrCtrl 167 memBlock.io.tlbCsr <> backend.io.mem.tlbCsr 168 memBlock.io.lsqio.rob <> backend.io.mem.robLsqIO 169 memBlock.io.lsqio.exceptionAddr.isStore := backend.io.mem.isStoreException 170 memBlock.io.itlb <> frontend.io.ptw 171 memBlock.io.redirect <> ctrlBlock.io.redirect 172 memBlock.io.rsfeedback <> exuBlocks(0).io.scheExtra.feedback.get 173 memBlock.io.csrCtrl <> csrioIn.customCtrl 174 memBlock.io.tlbCsr <> csrioIn.tlb 175 memBlock.io.lsqio.rob <> ctrlBlock.io.robio.lsq 176 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.uop.ctrl.commitType) 177 memBlock.io.debug_ls <> ctrlBlock.io.robio.debug_ls 178 memBlock.io.lsTopdownInfo <> ctrlBlock.io.robio.lsTopdownInfo 179 memBlock.io.l2_hint.valid := io.l2_hint.valid 180 memBlock.io.l2_hint.bits.sourceId := io.l2_hint.bits.sourceId 181 182 // if l2 prefetcher use stream prefetch, it should be placed in XSCore 183 io.l2_pf_enable := backend.io.csrCustomCtrl.l2_pf_enable 184 185 // Modules are reset one by one 186 val resetTree = ResetGenNode( 187 Seq( 188 ModuleNode(memBlock), 189 ResetGenNode(Seq( 190 ModuleNode(backend), 191 ResetGenNode(Seq( 192 ResetGenNode(Seq( 193 ModuleNode(frontend) 194 )) 195 )) 196 )) 197 ) 198 ) 199 200 ResetGen(resetTree, reset, !debugOpts.FPGAPlatform) 201 202} 203