1package xiangshan.backend.fu.wrapper 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import utils.XSError 7import xiangshan.backend.fu.FuConfig 8import xiangshan.backend.fu.vector.Bundles.VSew 9import xiangshan.backend.fu.vector.utils.VecDataSplitModule 10import xiangshan.backend.fu.vector.{Mgu, Utils, VecInfo, VecPipedFuncUnit, VecSrcTypeModule} 11import yunsuan.{VfaluType, VfpuType} 12import xiangshan.backend.fu.vector.Bundles.{VSew, Vl} 13import yunsuan.vector.VectorFloatAdder 14 15class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 16 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfalu OpType not supported") 17 18 // params alias 19 private val dataWidth = cfg.dataBits 20 private val dataWidthOfDataModule = 64 21 private val numVecModule = dataWidth / dataWidthOfDataModule 22 23 // io alias 24 private val opcode = fuOpType(4,0) 25 private val resWiden = fuOpType(5) 26 private val opbWiden = fuOpType(6) 27 28 // modules 29 private val vfalus = Seq.fill(numVecModule)(Module(new VectorFloatAdder)) 30 private val vs2Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 31 private val vs1Split = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 32 private val oldVdSplit = Module(new VecDataSplitModule(dataWidth, dataWidthOfDataModule)) 33 private val mgu = Module(new Mgu(dataWidth)) 34 35 /** 36 * In connection of [[vs2Split]], [[vs1Split]] and [[oldVdSplit]] 37 */ 38 vs2Split.io.inVecData := vs2 39 vs1Split.io.inVecData := vs1 40 oldVdSplit.io.inVecData := oldVd 41 42 /** 43 * [[vfalus]]'s in connection 44 */ 45 // Vec(vs2(31,0), vs2(63,32), vs2(95,64), vs2(127,96)) ==> 46 // Vec( 47 // Cat(vs2(95,64), vs2(31,0)), 48 // Cat(vs2(127,96), vs2(63,32)), 49 // ) 50 private val vs2GroupedVec: Vec[UInt] = VecInit(vs2Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 51 private val vs1GroupedVec: Vec[UInt] = VecInit(vs1Split.io.outVec32b.zipWithIndex.groupBy(_._2 % 2).map(x => x._1 -> x._2.map(_._1)).values.map(x => Cat(x.reverse)).toSeq) 52 private val resultData = Wire(Vec(numVecModule,UInt(dataWidthOfDataModule.W))) 53 private val fflagsData = Wire(Vec(numVecModule,UInt(20.W))) 54 private val srcMaskRShift = Wire(UInt((4 * numVecModule).W)) 55 56 def genMaskForMerge(inmask:UInt, sew:UInt, i:Int): UInt = { 57 val f64MaskNum = dataWidth / 64 58 val f32MaskNum = dataWidth / 32 59 val f16MaskNum = dataWidth / 16 60 val f64Mask = inmask(f64MaskNum-1,0) 61 val f32Mask = inmask(f32MaskNum-1,0) 62 val f16Mask = inmask(f16MaskNum-1,0) 63 val f64MaskI = Cat(0.U(3.W),f64Mask(i)) 64 val f32MaskI = Cat(0.U(2.W),f32Mask(2*i+1,2*i)) 65 val f16MaskI = f16Mask(4*i+3,4*i) 66 val outMask = Mux1H( 67 Seq( 68 (sew === 3.U) -> f64MaskI, 69 (sew === 2.U) -> f32MaskI, 70 (sew === 1.U) -> f16MaskI, 71 ) 72 ) 73 outMask 74 } 75 srcMaskRShift := (srcMask >> (vecCtrl.vuopIdx * (16.U >> vecCtrl.vsew)))(4 * numVecModule - 1, 0) 76 vfalus.zipWithIndex.foreach { 77 case (mod, i) => 78 mod.io.fp_a := Mux(opbWiden, vs1Split.io.outVec64b(i), vs2Split.io.outVec64b(i)) // very dirty TODO 79 mod.io.fp_b := Mux(opbWiden, vs2Split.io.outVec64b(i), vs1Split.io.outVec64b(i)) // very dirty TODO 80 mod.io.widen_a := Cat(vs2Split.io.outVec32b(i+numVecModule), vs2Split.io.outVec32b(i)) 81 mod.io.widen_b := Cat(vs1Split.io.outVec32b(i+numVecModule), vs1Split.io.outVec32b(i)) 82 mod.io.frs1 := 0.U // already vf -> vv 83 mod.io.is_frs1 := false.B // already vf -> vv 84 mod.io.mask := genMaskForMerge(inmask = srcMaskRShift, sew = vsew, i = i) 85 mod.io.uop_idx := vuopIdx(0) 86 mod.io.is_vec := true.B // Todo 87 mod.io.round_mode := frm 88 mod.io.fp_format := Mux(resWiden, vsew + 1.U, vsew) 89 mod.io.opb_widening := opbWiden 90 mod.io.res_widening := resWiden 91 mod.io.op_code := opcode 92 resultData(i) := mod.io.fp_result 93 fflagsData(i) := mod.io.fflags 94 } 95 val resultDataUInt = resultData.asUInt 96 val cmpResultWidth = dataWidth / 16 97 val cmpResult = Wire(Vec(cmpResultWidth, Bool())) 98 for (i <- 0 until cmpResultWidth) { 99 if(i == 0) { 100 cmpResult(i) := resultDataUInt(0) 101 } 102 else if(i < dataWidth / 64) { 103 cmpResult(i) := Mux1H( 104 Seq( 105 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i*16), 106 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i*32), 107 (outVecCtrl.vsew === 3.U) -> resultDataUInt(i*64) 108 ) 109 ) 110 } 111 else if(i < dataWidth / 32) { 112 cmpResult(i) := Mux1H( 113 Seq( 114 (outVecCtrl.vsew === 1.U) -> resultDataUInt(i * 16), 115 (outVecCtrl.vsew === 2.U) -> resultDataUInt(i * 32), 116 (outVecCtrl.vsew === 3.U) -> false.B 117 ) 118 ) 119 } 120 else if(i < dataWidth / 16) { 121 cmpResult(i) := Mux(outVecCtrl.vsew === 1.U, resultDataUInt(i*16), false.B) 122 } 123 } 124 125 val allFFlagsEn = Wire(Vec(4*numVecModule,Bool())) 126 val outSrcMaskRShift = Wire(UInt((4*numVecModule).W)) 127 outSrcMaskRShift := (outSrcMask >> (outVecCtrl.vuopIdx * (16.U >> outVecCtrl.vsew)))(4*numVecModule-1,0) 128 val f16FFlagsEn = outSrcMaskRShift 129 val f32FFlagsEn = Wire(Vec(numVecModule,UInt(4.W))) 130 for (i <- 0 until numVecModule){ 131 f32FFlagsEn(i) := Cat(Fill(2, 1.U),outSrcMaskRShift(2*i+1,2*i)) 132 } 133 val f64FFlagsEn = Wire(Vec(numVecModule, UInt(4.W))) 134 for (i <- 0 until numVecModule) { 135 f64FFlagsEn(i) := Cat(Fill(3, 1.U), outSrcMaskRShift(i)) 136 } 137 val fflagsEn= Mux1H( 138 Seq( 139 (outVecCtrl.vsew === 1.U) -> f16FFlagsEn.asUInt, 140 (outVecCtrl.vsew === 2.U) -> f32FFlagsEn.asUInt, 141 (outVecCtrl.vsew === 3.U) -> f64FFlagsEn.asUInt 142 ) 143 ) 144 allFFlagsEn := fflagsEn.asTypeOf(allFFlagsEn) 145 146 val allFFlags = fflagsData.asTypeOf(Vec(4*numVecModule,UInt(5.W))) 147 val outFFlags = allFFlagsEn.zip(allFFlags).map{ 148 case(en,fflags) => Mux(en, fflags, 0.U(5.W)) 149 }.reduce(_ | _) 150 io.out.bits.res.fflags.get := outFFlags 151 152 153 val cmpResultOldVd = Wire(UInt(cmpResultWidth.W)) 154 cmpResultOldVd := (outOldVd >> (outVecCtrl.vuopIdx * (16.U >> outVecCtrl.vsew)))(4*numVecModule-1,0) 155 val cmpResultForMgu = Wire(Vec(cmpResultWidth, Bool())) 156 for (i <- 0 until cmpResultWidth) { 157 cmpResultForMgu(i) := Mux(outSrcMaskRShift(i), cmpResult(i), Mux(outVecCtrl.vma, true.B, cmpResultOldVd(i))) 158 } 159 160 private val needNoMask = outCtrl.fuOpType === VfaluType.vfmerge 161 private val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 162 private val outEew = Mux(RegNext(resWiden), outVecCtrl.vsew + 1.U, outVecCtrl.vsew) 163 mgu.io.in.vd := Mux(outVecCtrl.isDstMask, Cat(0.U((dataWidth / 16 * 15).W), cmpResultForMgu.asUInt), resultDataUInt) 164 mgu.io.in.oldVd := outOldVd 165 mgu.io.in.mask := maskToMgu 166 mgu.io.in.info.ta := outVecCtrl.vta 167 mgu.io.in.info.ma := outVecCtrl.vma 168 mgu.io.in.info.vl := outVl 169 mgu.io.in.info.vstart := outVecCtrl.vstart 170 mgu.io.in.info.eew := outEew 171 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 172 mgu.io.in.info.narrow := outVecCtrl.isNarrow 173 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 174 io.out.bits.res.data := mgu.io.out.vd 175 176// io.out.bits.res.data := resultData.asUInt 177} 178 179class VFMgu(vlen:Int)(implicit p: Parameters) extends Module{ 180 val io = IO(new VFMguIO(vlen)) 181 182 val vd = io.in.vd 183 val oldvd = io.in.oldVd 184 val mask = io.in.mask 185 val vsew = io.in.info.eew 186 val num16bits = vlen / 16 187 188} 189 190class VFMguIO(vlen: Int)(implicit p: Parameters) extends Bundle { 191 val in = new Bundle { 192 val vd = Input(UInt(vlen.W)) 193 val oldVd = Input(UInt(vlen.W)) 194 val mask = Input(UInt(vlen.W)) 195 val info = Input(new VecInfo) 196 } 197 val out = new Bundle { 198 val vd = Output(UInt(vlen.W)) 199 } 200}