1package xiangshan.backend.decode.isa.bitfield 2 3import chisel3._ 4 5abstract class RiscvInst(bitWidth: Int) extends Bundle { 6 val inst: UInt = UInt(bitWidth.W) 7} 8 9class Riscv32BitInst extends RiscvInst(32) { 10 def ALL : UInt = inst 11 def OPCODE : UInt = inst( 6, 0) 12 def RD : UInt = inst(11, 7) 13 def FUNCT3 : UInt = inst(14, 12) 14 def RS1 : UInt = inst(19, 15) 15 def RS2 : UInt = inst(24, 20) 16 def FUNCT7 : UInt = inst(31, 25) 17} 18 19trait BitFieldsI { this: Riscv32BitInst => 20 def IMM12 : UInt = inst(31, 20) 21 def SHAMT6 : UInt = inst(25, 20) 22 def SHAMT5 : UInt = inst(24, 20) 23} 24 25trait BitFieldsS { this: Riscv32BitInst => 26 def IMM5 : UInt = inst(11, 7) 27 def IMM7 : UInt = inst(31, 25) 28} 29 30trait BitFieldsCSR { this: Riscv32BitInst => 31 def CSRIDX : UInt = inst(31, 20) 32 def CSRIMM : UInt = inst(19, 15) 33} 34 35trait BitFieldsFp { this: Riscv32BitInst => 36 def FD : UInt = inst(11, 7) 37 def FS1 : UInt = inst(19, 15) 38 def FS2 : UInt = inst(24, 20) 39 def FS3 : UInt = inst(31, 27) 40 def RM : UInt = inst(14, 12) // round mode 41 def CONV_SGN: UInt = inst(24, 20) 42 def FMT : UInt = inst(26, 25) 43 def TYP : UInt = inst(21, 20) 44} 45 46trait BitFieldsVec { this: Riscv32BitInst => 47 def VCATEGORY : UInt = inst(14, 12) 48 def NF : UInt = inst(31, 29) 49 def MEW : UInt = inst(28) 50 def MOP : UInt = inst(27, 26) 51 def VM : UInt = inst(25) 52 def LUMOP : UInt = inst(24, 20) 53 def SUMOP : UInt = inst(24, 20) 54 def WIDTH : UInt = inst(14, 12) 55 def VD : UInt = inst(11, 7) 56 def VS1 : UInt = inst(19, 15) 57 def VS2 : UInt = inst(24, 20) 58 def VS3 : UInt = inst(11, 7) 59 def FUNCT6 : UInt = inst(31 ,26) 60 def ZIMM_VSETVLI : UInt = inst(30, 20) 61 def ZIMM_VSETIVLI : UInt = inst(29, 20) 62 def UIMM_VSETIVLI : UInt = inst(19, 15) 63 def ZIMM_VTYPE : UInt = ZIMM_VSETIVLI(7, 0) 64 def IMM5_OPIVI : UInt = inst(19, 15) 65 66 def getInstVType : InstVType = { 67 val res = Wire(new InstVType) 68 res.vlmul := ZIMM_VSETVLI(2, 0) 69 res.vsew := ZIMM_VSETVLI(5, 3) 70 res.vta := ZIMM_VSETVLI(6) 71 res.vma := ZIMM_VSETVLI(7) 72 res 73 } 74 75 def isVecStore = { 76 this.OPCODE === "b0100111".U && (this.WIDTH === 0.U || this.WIDTH(2) === 1.B) 77 } 78} 79 80class XSInstBitFields extends Riscv32BitInst 81 with BitFieldsI 82 with BitFieldsS 83 with BitFieldsCSR 84 with BitFieldsFp 85 with BitFieldsVec 86 87class InstVType extends Bundle { 88 val vma = Bool() 89 val vta = Bool() 90 val vsew = UInt(3.W) 91 val vlmul = UInt(3.W) 92} 93 94