1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.fu.{PFEvent, PMP, PMPChecker,PMPReqBundle} 26import xiangshan.cache.mmu._ 27import xiangshan.frontend.icache._ 28 29 30class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 31 32 val instrUncache = LazyModule(new InstrUncache()) 33 val icache = LazyModule(new ICache()) 34 35 lazy val module = new FrontendImp(this) 36} 37 38 39class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 40 with HasXSParameter 41 with HasPerfEvents 42{ 43 val io = IO(new Bundle() { 44 val hartId = Input(UInt(8.W)) 45 val reset_vector = Input(UInt(PAddrBits.W)) 46 val fencei = Input(Bool()) 47 val ptw = new VectorTlbPtwIO(coreParams.itlbPortNum) 48 val backend = new FrontendToCtrlIO 49 val sfence = Input(new SfenceBundle) 50 val tlbCsr = Input(new TlbCsrBundle) 51 val csrCtrl = Input(new CustomCSRCtrlIO) 52 val csrUpdate = new DistributedCSRUpdateReq 53 val error = new L1CacheErrorInfo 54 val frontendInfo = new Bundle { 55 val ibufFull = Output(Bool()) 56 val bpuInfo = new Bundle { 57 val bpRight = Output(UInt(XLEN.W)) 58 val bpWrong = Output(UInt(XLEN.W)) 59 } 60 } 61 }) 62 63 //decouped-frontend modules 64 val instrUncache = outer.instrUncache.module 65 val icache = outer.icache.module 66 val bpu = Module(new Predictor) 67 val ifu = Module(new NewIFU) 68 val ibuffer = Module(new Ibuffer) 69 val ftq = Module(new Ftq) 70 71 val needFlush = RegNext(io.backend.toFtq.redirect.valid) 72 val FlushControlRedirect = RegNext(io.backend.toFtq.redirect.bits.debugIsCtrl) 73 val FlushMemVioRedirect = RegNext(io.backend.toFtq.redirect.bits.debugIsMemVio) 74 val FlushControlBTBMiss = Wire(Bool()) 75 val FlushTAGEMiss = Wire(Bool()) 76 val FlushSCMiss = Wire(Bool()) 77 val FlushITTAGEMiss = Wire(Bool()) 78 val FlushRASMiss = Wire(Bool()) 79 80 val tlbCsr = DelayN(io.tlbCsr, 2) 81 val csrCtrl = DelayN(io.csrCtrl, 2) 82 val sfence = RegNext(RegNext(io.sfence)) 83 84 // trigger 85 ifu.io.frontendTrigger := csrCtrl.frontend_trigger 86 val triggerEn = csrCtrl.trigger_enable 87 ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8)) 88 89 // bpu ctrl 90 bpu.io.ctrl := csrCtrl.bp_ctrl 91 bpu.io.reset_vector := io.reset_vector 92 93// pmp 94 val prefetchPipeNum = ICacheParameters().prefetchPipeNum 95 val pmp = Module(new PMP()) 96 val pmp_check = VecInit(Seq.fill(coreParams.ipmpPortNum)(Module(new PMPChecker(3, sameCycle = true)).io)) 97 pmp.io.distribute_csr := csrCtrl.distribute_csr 98 val pmp_req_vec = Wire(Vec(coreParams.ipmpPortNum, Valid(new PMPReqBundle()))) 99 (0 until 2 + prefetchPipeNum).foreach(i => pmp_req_vec(i) <> icache.io.pmp(i).req) 100 pmp_req_vec.last <> ifu.io.pmp.req 101 102 for (i <- pmp_check.indices) { 103 pmp_check(i).apply(tlbCsr.priv.imode, pmp.io.pmp, pmp.io.pma, pmp_req_vec(i)) 104 } 105 (0 until 2 + prefetchPipeNum).foreach(i => icache.io.pmp(i).resp <> pmp_check(i).resp) 106 ifu.io.pmp.resp <> pmp_check.last.resp 107 108 val itlb = Module(new TLB(coreParams.itlbPortNum, nRespDups = 1, 109 Seq(true, true) ++ Seq.fill(prefetchPipeNum)(false) ++ Seq(true), itlbParams)) 110 itlb.io.requestor.take(2 + prefetchPipeNum) zip icache.io.itlb foreach {case (a,b) => a <> b} 111 itlb.io.requestor.last <> ifu.io.iTLBInter // mmio may need re-tlb, blocked 112 itlb.io.base_connect(io.sfence, tlbCsr) 113 io.ptw.connect(itlb.io.ptw) 114 itlb.io.ptw_replenish <> DontCare 115 itlb.io.flushPipe.map(_ := needFlush) 116 117 icache.io.prefetch <> ftq.io.toPrefetch 118 119 120 //IFU-Ftq 121 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 122 ftq.io.toIfu.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready 123 124 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 125 bpu.io.ftq_to_bpu <> ftq.io.toBpu 126 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 127 128 ftq.io.mmioCommitRead <> ifu.io.mmioCommitRead 129 //IFU-ICache 130 131 icache.io.fetch.req <> ftq.io.toICache.req 132 ftq.io.toICache.req.ready := ifu.io.ftqInter.fromFtq.req.ready && icache.io.fetch.req.ready 133 134 ifu.io.icacheInter.resp <> icache.io.fetch.resp 135 ifu.io.icacheInter.icacheReady := icache.io.toIFU 136 ifu.io.icacheInter.topdownIcacheMiss := icache.io.fetch.topdownIcacheMiss 137 ifu.io.icacheInter.topdownItlbMiss := icache.io.fetch.topdownItlbMiss 138 icache.io.stop := ifu.io.icacheStop 139 140 ifu.io.icachePerfInfo := icache.io.perfInfo 141 142 icache.io.csr.distribute_csr <> csrCtrl.distribute_csr 143 io.csrUpdate := RegNext(icache.io.csr.update) 144 145 icache.io.csr_pf_enable := RegNext(csrCtrl.l1I_pf_enable) 146 icache.io.csr_parity_enable := RegNext(csrCtrl.icache_parity_enable) 147 148 icache.io.fencei := io.fencei 149 150 //IFU-Ibuffer 151 ifu.io.toIbuffer <> ibuffer.io.in 152 153 ftq.io.fromBackend <> io.backend.toFtq 154 io.backend.fromFtq <> ftq.io.toBackend 155 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 156 157 ifu.io.rob_commits <> io.backend.toFtq.rob_commits 158 159 ibuffer.io.flush := needFlush 160 ibuffer.io.ControlRedirect := FlushControlRedirect 161 ibuffer.io.MemVioRedirect := FlushMemVioRedirect 162 ibuffer.io.ControlBTBMissBubble := FlushControlBTBMiss 163 ibuffer.io.TAGEMissBubble := FlushTAGEMiss 164 ibuffer.io.SCMissBubble := FlushSCMiss 165 ibuffer.io.ITTAGEMissBubble := FlushITTAGEMiss 166 ibuffer.io.RASMissBubble := FlushRASMiss 167 168 FlushControlBTBMiss := ftq.io.ControlBTBMissBubble 169 FlushTAGEMiss := ftq.io.TAGEMissBubble 170 FlushSCMiss := ftq.io.SCMissBubble 171 FlushITTAGEMiss := ftq.io.ITTAGEMissBubble 172 FlushRASMiss := ftq.io.RASMissBubble 173 174 io.backend.cfVec <> ibuffer.io.out 175 io.backend.stallReason <> ibuffer.io.stallReason 176 dontTouch(io.backend.stallReason) 177 178 instrUncache.io.req <> ifu.io.uncacheInter.toUncache 179 ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 180 instrUncache.io.flush := false.B 181 io.error <> RegNext(RegNext(icache.io.error)) 182 183 icache.io.hartId := io.hartId 184 185 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 186 XSPerfAccumulate("FrontendBubble", frontendBubble) 187 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 188 189 // PFEvent 190 val pfevent = Module(new PFEvent) 191 pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 192 val csrevents = pfevent.io.hpmevent.take(8) 193 194 val allPerfEvents = Seq(ifu, ibuffer, icache, ftq, bpu).flatMap(_.getPerf) 195 override val perfEvents = HPerfMonitor(csrevents, allPerfEvents).getPerfEvents 196 generatePerfEvent() 197} 198