xref: /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala (revision 26af847e669bb208507278eafc6ebe52f03b0d19) 
1package xiangshan.backend.fu.wrapper
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.decode._
7import utils.XSError
8import xiangshan.backend.fu.FuConfig
9import xiangshan.backend.fu.vector.{Mgu, VecPipedFuncUnit}
10import xiangshan.ExceptionNO
11import yunsuan.VfpuType
12import yunsuan.vector.VectorConvert.VectorCvt
13import yunsuan.util._
14
15
16class VCVT(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) {
17  XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfcvt OpType not supported")
18
19  // params alias
20  private val dataWidth = cfg.dataBits
21  private val dataWidthOfDataModule = 64
22  private val numVecModule = dataWidth / dataWidthOfDataModule
23
24  // io alias
25  private val opcode = fuOpType(8, 0)
26  private val sew = vsew
27
28  private val isRtz = opcode(2) & opcode(1)
29  private val isRod = opcode(2) & !opcode(1) & opcode(0)
30  private val isFrm = !isRtz && !isRod
31  private val vfcvtRm = Mux1H(
32    Seq(isRtz, isRod, isFrm),
33    Seq(1.U, 6.U, rm)
34  )
35
36  private val lmul = vlmul // -3->3 => 1/8 ->8
37
38  val widen = opcode(4, 3) // 0->single 1->widen 2->norrow => width of result
39  val isSingleCvt = !widen(1) & !widen(0)
40  val isWidenCvt = !widen(1) & widen(0)
41  val isNarrowCvt = widen(1) & !widen(0)
42  val fire = io.in.valid
43  val fireReg = GatedValidRegNext(fire)
44
45  // output width 8， 16， 32， 64
46  val output1H = Wire(UInt(4.W))
47  output1H := chisel3.util.experimental.decode.decoder(
48    widen ## sew,
49    TruthTable(
50      Seq(
51        BitPat("b00_01") -> BitPat("b0010"), // 16
52        BitPat("b00_10") -> BitPat("b0100"), // 32
53        BitPat("b00_11") -> BitPat("b1000"), // 64
54
55        BitPat("b01_00") -> BitPat("b0010"), // 16
56        BitPat("b01_01") -> BitPat("b0100"), // 32
57        BitPat("b01_10") -> BitPat("b1000"), // 64
58
59        BitPat("b10_00") -> BitPat("b0001"), // 8
60        BitPat("b10_01") -> BitPat("b0010"), // 16
61        BitPat("b10_10") -> BitPat("b0100"), // 32
62      ),
63      BitPat.N(4)
64    )
65  )
66  if(backendParams.debugEn) {
67    dontTouch(output1H)
68  }
69  val outputWidth1H = output1H
70  val outIs32bits = RegNext(RegNext(outputWidth1H(2)))
71  val outIsInt = !outCtrl.fuOpType(6)
72  val outIsMvInst = outCtrl.fuOpType(8)
73
74  val outEew = RegEnable(RegEnable(Mux1H(output1H, Seq(0,1,2,3).map(i => i.U)), fire), fireReg)
75  private val needNoMask = outVecCtrl.fpu.isFpToVecInst
76  val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask)
77
78  // modules
79  private val vfcvt = Module(new VectorCvtTop(dataWidth, dataWidthOfDataModule))
80  private val mgu = Module(new Mgu(dataWidth))
81
82  val vs2Vec = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W)))
83  vs2Vec := vs2.asTypeOf(vs2Vec)
84
85  /**
86   * [[vfcvt]]'s in connection
87   */
88  vfcvt.uopIdx := vuopIdx(0)
89  vfcvt.src := vs2Vec
90  vfcvt.opType := opcode(7,0)
91  vfcvt.sew := sew
92  vfcvt.rm := vfcvtRm
93  vfcvt.outputWidth1H := outputWidth1H
94  vfcvt.isWiden := isWidenCvt
95  vfcvt.isNarrow := isNarrowCvt
96  vfcvt.fire := fire
97  val vfcvtResult = vfcvt.io.result
98  val vfcvtFflags = vfcvt.io.fflags
99
100  /** fflags:
101   */
102  val eNum1H = chisel3.util.experimental.decode.decoder(sew ## (isWidenCvt || isNarrowCvt),
103    TruthTable(
104      Seq(                     // 8, 4, 2, 1
105        BitPat("b001") -> BitPat("b1000"), //8
106        BitPat("b010") -> BitPat("b1000"), //8
107        BitPat("b011") -> BitPat("b0100"), //4
108        BitPat("b100") -> BitPat("b0100"), //4
109        BitPat("b101") -> BitPat("b0010"), //2
110        BitPat("b110") -> BitPat("b0010"), //2
111      ),
112      BitPat.N(4)
113    )
114  )
115  val eNumMax1H = Mux(lmul.head(1).asBool, eNum1H >> ((~lmul.tail(1)).asUInt +1.U), eNum1H << lmul.tail(1)).asUInt(6, 0)
116  val eNumMax = Mux1H(eNumMax1H, Seq(1,2,4,8,16,32,64).map(i => i.U)) //only for cvt intr, don't exist 128 in cvt
117  val vlForFflags = Mux(vecCtrl.fpu.isFpToVecInst, 1.U, vl)
118  val eNumEffectIdx = Mux(vlForFflags > eNumMax, eNumMax, vlForFflags)
119
120  val eNum = Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num =>num.U))
121  val eStart = vuopIdx * eNum
122  val maskForFflags = Mux(vecCtrl.fpu.isFpToVecInst, allMaskTrue, srcMask)
123  val maskPart = maskForFflags >> eStart
124  val mask =  Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num => maskPart(num-1, 0)))
125  val fflagsEn = Wire(Vec(4 * numVecModule, Bool()))
126
127  fflagsEn := mask.asBools.zipWithIndex.map{case(mask, i) => mask & (eNumEffectIdx > eStart + i.U) }
128
129  val fflagsEnCycle2 = RegEnable(RegEnable(fflagsEn, fire), fireReg)
130  val fflagsAll = Wire(Vec(8, UInt(5.W)))
131  fflagsAll := vfcvtFflags.asTypeOf(fflagsAll)
132  val fflags = fflagsEnCycle2.zip(fflagsAll).map{case(en, fflag) => Mux(en, fflag, 0.U(5.W))}.reduce(_ | _)
133  io.out.bits.res.fflags.get := Mux(outIsMvInst, 0.U, fflags)
134
135
136  /**
137   * [[mgu]]'s in connection
138   */
139  val resultDataUInt = Wire(UInt(dataWidth.W))
140  resultDataUInt := vfcvtResult
141
142  private val narrow = RegEnable(RegEnable(isNarrowCvt, fire), fireReg)
143  private val narrowNeedCat = outVecCtrl.vuopIdx(0).asBool && narrow
144  private val outNarrowVd = Mux(narrowNeedCat, Cat(resultDataUInt(dataWidth / 2 - 1, 0), outOldVd(dataWidth / 2 - 1, 0)), resultDataUInt)
145
146  mgu.io.in.vd := resultDataUInt
147  mgu.io.in.vd := Mux(narrow, outNarrowVd, resultDataUInt)
148  mgu.io.in.oldVd := outOldVd
149  mgu.io.in.mask := maskToMgu
150  mgu.io.in.info.ta := outVecCtrl.vta
151  mgu.io.in.info.ma := outVecCtrl.vma
152  mgu.io.in.info.vl := Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl)
153  mgu.io.in.info.vlmul := outVecCtrl.vlmul
154  mgu.io.in.info.valid := io.out.valid
155  mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart)
156  mgu.io.in.info.eew := outEew
157  mgu.io.in.info.vsew := outVecCtrl.vsew
158  mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx
159  mgu.io.in.info.narrow := narrow
160  mgu.io.in.info.dstMask := outVecCtrl.isDstMask
161  mgu.io.in.isIndexedVls := false.B
162
163  // for scalar f2i cvt inst
164  val isFp2VecForInt = outVecCtrl.fpu.isFpToVecInst && outIs32bits && outIsInt
165  // for f2i mv inst
166  val result = Mux(outIsMvInst, RegNext(RegNext(vs2.tail(64))), mgu.io.out.vd)
167
168  io.out.bits.res.data := Mux(isFp2VecForInt,
169    Fill(32, result(31)) ## result(31, 0),
170    result
171  )
172  io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal
173}
174
175class VectorCvtTopIO(vlen: Int, xlen: Int) extends Bundle{
176  val fire = Input(Bool())
177  val uopIdx = Input(Bool())
178  val src = Input(Vec(vlen / xlen, UInt(xlen.W)))
179  val opType = Input(UInt(8.W))
180  val sew = Input(UInt(2.W))
181  val rm = Input(UInt(3.W))
182  val outputWidth1H = Input(UInt(4.W))
183  val isWiden = Input(Bool())
184  val isNarrow = Input(Bool())
185
186  val result = Output(UInt(vlen.W))
187  val fflags = Output(UInt((vlen/16*5).W))
188}
189
190
191
192//according to uopindex, 1: high64 0:low64
193class VectorCvtTop(vlen: Int, xlen: Int) extends Module{
194  val io = IO(new VectorCvtTopIO(vlen, xlen))
195
196  val (fire, uopIdx, src, opType, sew, rm, outputWidth1H, isWiden, isNarrow) = (
197    io.fire, io.uopIdx, io.src, io.opType, io.sew, io.rm, io.outputWidth1H, io.isWiden, io.isNarrow
198  )
199  val fireReg = GatedValidRegNext(fire)
200
201  val in0 = Mux(isWiden,
202    Mux(uopIdx, src(1).tail(32), src(0).tail(32)),
203    src(0)
204  )
205
206  val in1 = Mux(isWiden,
207    Mux(uopIdx, src(1).head(32), src(0).head(32)),
208    src(1)
209  )
210
211  val vectorCvt0 = Module(new VectorCvt(xlen))
212  vectorCvt0.fire := fire
213  vectorCvt0.src := in0
214  vectorCvt0.opType := opType
215  vectorCvt0.sew := sew
216  vectorCvt0.rm := rm
217
218  val vectorCvt1 = Module(new VectorCvt(xlen))
219  vectorCvt1.fire := fire
220  vectorCvt1.src := in1
221  vectorCvt1.opType := opType
222  vectorCvt1.sew := sew
223  vectorCvt1.rm := rm
224
225  val isNarrowCycle2 = RegEnable(RegEnable(isNarrow, fire), fireReg)
226  val outputWidth1HCycle2 = RegEnable(RegEnable(outputWidth1H, fire), fireReg)
227
228  //cycle2
229  io.result := Mux(isNarrowCycle2,
230    vectorCvt1.io.result.tail(32) ## vectorCvt0.io.result.tail(32),
231    vectorCvt1.io.result ## vectorCvt0.io.result)
232
233  io.fflags := Mux1H(outputWidth1HCycle2, Seq(
234    vectorCvt1.io.fflags ## vectorCvt0.io.fflags,
235    Mux(isNarrowCycle2, vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10), vectorCvt1.io.fflags ## vectorCvt0.io.fflags),
236    Mux(isNarrowCycle2, vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0), vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10)),
237    vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0)
238  ))
239}
240
241
242