chore(fu): delete redundant code in VCVT (#4328)

fix(VCVT): disable logic about scalar move instructions. (#3607)

feat(riscv64): Support RISC-V Zfa extension

* Support fli.{h.s.d}, fminm.{h.s.d}, fmaxm.{h.s.d}
* Support fround.{h.s.d}, froundnx.{h.s.d}, fcvtmod.w.d
* Support fleq.{h.s.d}, fltq.{h.s.d}

FU: fix generation of fflags in VCVT fu

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

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rv64v: fix the wrong dependency caused by uop split

FuConfig: split dataBits into destDataBits and srcDataBits for distinguish input and output data width

float: use VCVT module for all fcvt instructions
Co-authored-by: chengguanghui <[email protected]>

float: fix read rouding mode which is ecnoded in the float instruction

FU: fix vfcvt & bump yunsuan

Backend: add clock gating to valid singal

rv64v: add fire sign as enable of RegNext

backend: control dontTouch opcode by debugEn

rv64v: fix data merge for fp narrow convert instructions

Mgu: use sew as element width instead of eew for indexed loads/stores

vector: convert mgu's assertion to EX_II

fix merge error

bump & rm useless code

vfcvt rtl: fixed cvt fu

bump yunsuan