1package xiangshan.backend.fu.wrapper 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.decode._ 7import utils.XSError 8import xiangshan.backend.fu.FuConfig 9import xiangshan.backend.fu.vector.{Mgu, VecPipedFuncUnit} 10import xiangshan.ExceptionNO 11import yunsuan.VfpuType 12import yunsuan.vector.VectorConvert.VectorCvt 13 14 15class VCVT(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) { 16 XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfcvt OpType not supported") 17 18 // params alias 19 private val dataWidth = cfg.dataBits 20 private val dataWidthOfDataModule = 64 21 private val numVecModule = dataWidth / dataWidthOfDataModule 22 23 // io alias 24 private val opcode = fuOpType(7, 0) 25 private val sew = vsew 26 27 private val isRtz = opcode(2) & opcode(1) 28 private val isRod = opcode(2) & !opcode(1) & opcode(0) 29 private val isFrm = !isRtz && !isRod 30 private val rm = Mux1H( 31 Seq(isRtz, isRod, isFrm), 32 Seq(1.U, 6.U, frm) 33 ) 34 35 private val lmul = vlmul // -3->3 => 1/8 ->8 36 37 val widen = opcode(4, 3) // 0->single 1->widen 2->norrow => width of result 38 val isSingleCvt = !widen(1) & !widen(0) 39 val isWidenCvt = !widen(1) & widen(0) 40 val isNarrowCvt = widen(1) & !widen(0) 41 val fire = io.in.valid 42 val fireReg = RegNext(fire) 43 44 // output width 8， 16， 32， 64 45 val output1H = Wire(UInt(4.W)) 46 output1H := chisel3.util.experimental.decode.decoder( 47 widen ## sew, 48 TruthTable( 49 Seq( 50 BitPat("b00_01") -> BitPat("b0010"), // 16 51 BitPat("b00_10") -> BitPat("b0100"), // 32 52 BitPat("b00_11") -> BitPat("b1000"), // 64 53 54 BitPat("b01_00") -> BitPat("b0010"), // 16 55 BitPat("b01_01") -> BitPat("b0100"), // 32 56 BitPat("b01_10") -> BitPat("b1000"), // 64 57 58 BitPat("b10_00") -> BitPat("b0001"), // 8 59 BitPat("b10_01") -> BitPat("b0010"), // 16 60 BitPat("b10_10") -> BitPat("b0100"), // 32 61 ), 62 BitPat.N(4) 63 ) 64 ) 65 if(backendParams.debugEn) { 66 dontTouch(output1H) 67 } 68 val outputWidth1H = output1H 69 70 val outEew = RegEnable(RegEnable(Mux1H(output1H, Seq(0,1,2,3).map(i => i.U)), fire), fireReg) 71 private val needNoMask = outVecCtrl.fpu.isFpToVecInst 72 val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask) 73 74 // modules 75 private val vfcvt = Module(new VectorCvtTop(dataWidth, dataWidthOfDataModule)) 76 private val mgu = Module(new Mgu(dataWidth)) 77 78 val vs2Vec = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W))) 79 vs2Vec := vs2.asTypeOf(vs2Vec) 80 81 /** 82 * [[vfcvt]]'s in connection 83 */ 84 vfcvt.uopIdx := vuopIdx(0) 85 vfcvt.src := vs2Vec 86 vfcvt.opType := opcode 87 vfcvt.sew := sew 88 vfcvt.rm := rm 89 vfcvt.outputWidth1H := outputWidth1H 90 vfcvt.isWiden := isWidenCvt 91 vfcvt.isNarrow := isNarrowCvt 92 vfcvt.fire := fire 93 val vfcvtResult = vfcvt.io.result 94 val vfcvtFflags = vfcvt.io.fflags 95 96 /** fflags: 97 */ 98 val eNum1H = chisel3.util.experimental.decode.decoder(sew ## (isWidenCvt || isNarrowCvt), 99 TruthTable( 100 Seq( // 8, 4, 2, 1 101 BitPat("b001") -> BitPat("b1000"), //8 102 BitPat("b010") -> BitPat("b1000"), //8 103 BitPat("b011") -> BitPat("b0100"), //4 104 BitPat("b100") -> BitPat("b0100"), //4 105 BitPat("b101") -> BitPat("b0010"), //2 106 BitPat("b110") -> BitPat("b0010"), //2 107 ), 108 BitPat.N(4) 109 ) 110 ) 111 val eNumMax1H = Mux(lmul.head(1).asBool, eNum1H >> ((~lmul.tail(1)).asUInt +1.U), eNum1H << lmul.tail(1)).asUInt(6, 0) 112 val eNumMax = Mux1H(eNumMax1H, Seq(1,2,4,8,16,32,64).map(i => i.U)) //only for cvt intr, don't exist 128 in cvt 113 val eNumEffectIdx = Mux(vl > eNumMax, eNumMax, vl) 114 115 val eNum = Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num =>num.U)) 116 val eStart = vuopIdx * eNum 117 val maskPart = srcMask >> eStart 118 val mask = Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num => maskPart(num-1, 0))) 119 val fflagsEn = Wire(Vec(4 * numVecModule, Bool())) 120 121 fflagsEn := mask.asBools.zipWithIndex.map{case(mask, i) => mask & (eNumEffectIdx > eStart + i.U) } 122 123 val fflagsEnCycle2 = RegEnable(RegEnable(fflagsEn, fire), fireReg) 124 val fflagsAll = Wire(Vec(8, UInt(5.W))) 125 fflagsAll := vfcvtFflags.asTypeOf(fflagsAll) 126 val fflags = fflagsEnCycle2.zip(fflagsAll).map{case(en, fflag) => Mux(en, fflag, 0.U(5.W))}.reduce(_ | _) 127 io.out.bits.res.fflags.get := fflags 128 129 130 /** 131 * [[mgu]]'s in connection 132 */ 133 val resultDataUInt = Wire(UInt(dataWidth.W)) 134 resultDataUInt := vfcvtResult 135 136 private val narrow = RegEnable(RegEnable(isNarrowCvt, fire), fireReg) 137 private val narrowNeedCat = outVecCtrl.vuopIdx(0).asBool && narrow 138 private val outNarrowVd = Mux(narrowNeedCat, Cat(resultDataUInt(dataWidth / 2 - 1, 0), outOldVd(dataWidth / 2 - 1, 0)), resultDataUInt) 139 140 mgu.io.in.vd := resultDataUInt 141 mgu.io.in.vd := Mux(narrow, outNarrowVd, resultDataUInt) 142 mgu.io.in.oldVd := outOldVd 143 mgu.io.in.mask := maskToMgu 144 mgu.io.in.info.ta := outVecCtrl.vta 145 mgu.io.in.info.ma := outVecCtrl.vma 146 mgu.io.in.info.vl := Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl) 147 mgu.io.in.info.vlmul := outVecCtrl.vlmul 148 mgu.io.in.info.valid := io.out.valid 149 mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart) 150 mgu.io.in.info.eew := outEew 151 mgu.io.in.info.vsew := outVecCtrl.vsew 152 mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx 153 mgu.io.in.info.narrow := narrow 154 mgu.io.in.info.dstMask := outVecCtrl.isDstMask 155 mgu.io.in.isIndexedVls := false.B 156 157 io.out.bits.res.data := mgu.io.out.vd 158 io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal 159} 160 161class VectorCvtTopIO(vlen: Int, xlen: Int) extends Bundle{ 162 val fire = Input(Bool()) 163 val uopIdx = Input(Bool()) 164 val src = Input(Vec(vlen / xlen, UInt(xlen.W))) 165 val opType = Input(UInt(8.W)) 166 val sew = Input(UInt(2.W)) 167 val rm = Input(UInt(3.W)) 168 val outputWidth1H = Input(UInt(4.W)) 169 val isWiden = Input(Bool()) 170 val isNarrow = Input(Bool()) 171 172 val result = Output(UInt(vlen.W)) 173 val fflags = Output(UInt((vlen/16*5).W)) 174} 175 176 177 178//according to uopindex, 1: high64 0:low64 179class VectorCvtTop(vlen: Int, xlen: Int) extends Module{ 180 val io = IO(new VectorCvtTopIO(vlen, xlen)) 181 182 val (fire, uopIdx, src, opType, sew, rm, outputWidth1H, isWiden, isNarrow) = ( 183 io.fire, io.uopIdx, io.src, io.opType, io.sew, io.rm, io.outputWidth1H, io.isWiden, io.isNarrow 184 ) 185 val fireReg = RegNext(fire) 186 187 val in0 = Mux(isWiden, 188 Mux(uopIdx, src(1).tail(32), src(0).tail(32)), 189 src(0) 190 ) 191 192 val in1 = Mux(isWiden, 193 Mux(uopIdx, src(1).head(32), src(0).head(32)), 194 src(1) 195 ) 196 197 val vectorCvt0 = Module(new VectorCvt(xlen)) 198 vectorCvt0.fire := fire 199 vectorCvt0.src := in0 200 vectorCvt0.opType := opType 201 vectorCvt0.sew := sew 202 vectorCvt0.rm := rm 203 204 val vectorCvt1 = Module(new VectorCvt(xlen)) 205 vectorCvt1.fire := fire 206 vectorCvt1.src := in1 207 vectorCvt1.opType := opType 208 vectorCvt1.sew := sew 209 vectorCvt1.rm := rm 210 211 val isNarrowCycle2 = RegEnable(RegEnable(isNarrow, fire), fireReg) 212 val outputWidth1HCycle2 = RegEnable(RegEnable(outputWidth1H, fire), fireReg) 213 214 //cycle2 215 io.result := Mux(isNarrowCycle2, 216 vectorCvt1.io.result.tail(32) ## vectorCvt0.io.result.tail(32), 217 vectorCvt1.io.result ## vectorCvt0.io.result) 218 219 io.fflags := Mux1H(outputWidth1HCycle2, Seq( 220 vectorCvt1.io.fflags ## vectorCvt0.io.fflags, 221 Mux(isNarrowCycle2, vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10), vectorCvt1.io.fflags ## vectorCvt0.io.fflags), 222 Mux(isNarrowCycle2, vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0), vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10)), 223 vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0) 224 )) 225} 226 227 228