xref: /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala (revision 83ba63b34cf09b33c0a9e1b3203138e51af4491b) 
1package xiangshan.backend.fu.wrapper
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.decode._
7import utils.XSError
8import xiangshan.backend.fu.FuConfig
9import xiangshan.backend.fu.vector.{Mgu, VecPipedFuncUnit}
10import yunsuan.VfpuType
11import yunsuan.vector.VectorConvert.VectorCvt
12
13
14class VCVT(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) {
15  XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VfpuType.dummy, "Vfcvt OpType not supported")
16
17  // params alias
18  private val dataWidth = cfg.dataBits
19  private val dataWidthOfDataModule = 64
20  private val numVecModule = dataWidth / dataWidthOfDataModule
21
22  // io alias
23  private val opcode = fuOpType(7, 0)
24  private val sew = vsew
25
26  private val isRtz = opcode(2) & opcode(1)
27  private val isRod = opcode(2) & !opcode(1) & opcode(0)
28  private val isFrm = !isRtz && !isRod
29  private val rm = Mux1H(
30    Seq(isRtz, isRod, isFrm),
31    Seq(1.U, 6.U, frm)
32  )
33
34  private val lmul = vlmul // -3->3 => 1/8 ->8
35
36  val widen = opcode(4, 3) // 0->single 1->widen 2->norrow => width of result
37  val isSingleCvt = !widen(1) & !widen(0)
38  val isWidenCvt = !widen(1) & widen(0)
39  val isNarrowCvt = widen(1) & !widen(0)
40
41  // output width 8， 16， 32， 64
42  val output1H = Wire(UInt(4.W))
43  output1H := chisel3.util.experimental.decode.decoder(
44    widen ## sew,
45    TruthTable(
46      Seq(
47        BitPat("b00_01") -> BitPat("b0010"), // 16
48        BitPat("b00_10") -> BitPat("b0100"), // 32
49        BitPat("b00_11") -> BitPat("b1000"), // 64
50
51        BitPat("b01_00") -> BitPat("b0010"), // 16
52        BitPat("b01_01") -> BitPat("b0100"), // 32
53        BitPat("b01_10") -> BitPat("b1000"), // 64
54
55        BitPat("b10_00") -> BitPat("b0001"), // 8
56        BitPat("b10_01") -> BitPat("b0010"), // 16
57        BitPat("b10_10") -> BitPat("b0100"), // 32
58      ),
59      BitPat.N(4)
60    )
61  )
62  dontTouch(output1H)
63  val outputWidth1H = output1H
64
65  val outEew = RegNext(RegNext(Mux1H(output1H, Seq(0,1,2,3).map(i => i.U))))
66  private val needNoMask = outVecCtrl.fpu.isFpToVecInst
67  val maskToMgu = Mux(needNoMask, allMaskTrue, outSrcMask)
68
69  // modules
70  private val vfcvt = Module(new VectorCvtTop(dataWidth, dataWidthOfDataModule))
71  private val mgu = Module(new Mgu(dataWidth))
72
73  val vs2Vec = Wire(Vec(numVecModule, UInt(dataWidthOfDataModule.W)))
74  vs2Vec := vs2.asTypeOf(vs2Vec)
75
76  /**
77   * [[vfcvt]]'s in connection
78   */
79  vfcvt.uopIdx := vuopIdx(0)
80  vfcvt.src := vs2Vec
81  vfcvt.opType := opcode
82  vfcvt.sew := sew
83  vfcvt.rm := rm
84  vfcvt.outputWidth1H := outputWidth1H
85  vfcvt.isWiden := isWidenCvt
86  vfcvt.isNarrow := isNarrowCvt
87  val vfcvtResult = vfcvt.io.result
88  val vfcvtFflags = vfcvt.io.fflags
89
90  /** fflags:
91   */
92  val eNum1H = chisel3.util.experimental.decode.decoder(sew ## (isWidenCvt || isNarrowCvt),
93    TruthTable(
94      Seq(                     // 8, 4, 2, 1
95        BitPat("b001") -> BitPat("b1000"), //8
96        BitPat("b010") -> BitPat("b1000"), //8
97        BitPat("b011") -> BitPat("b0100"), //4
98        BitPat("b100") -> BitPat("b0100"), //4
99        BitPat("b101") -> BitPat("b0010"), //2
100        BitPat("b110") -> BitPat("b0010"), //2
101      ),
102      BitPat.N(4)
103    )
104  )
105  val eNumMax1H = Mux(lmul.head(1).asBool, eNum1H >> ((~lmul.tail(1)).asUInt +1.U), eNum1H << lmul.tail(1)).asUInt(6, 0)
106  val eNumMax = Mux1H(eNumMax1H, Seq(1,2,4,8,16,32,64).map(i => i.U)) //only for cvt intr, don't exist 128 in cvt
107  val eNumEffectIdx = Mux(vl > eNumMax, eNumMax, vl)
108
109  val eNum = Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num =>num.U))
110  val eStart = vuopIdx * eNum
111  val maskPart = srcMask >> eStart
112  val mask =  Mux1H(eNum1H, Seq(1, 2, 4, 8).map(num => maskPart(num-1, 0)))
113  val fflagsEn = Wire(Vec(4 * numVecModule, Bool()))
114
115  fflagsEn := mask.asBools.zipWithIndex.map{case(mask, i) => mask & (eNumEffectIdx > eStart + i.U) }
116
117  val fflagsEnCycle2 = RegNext(RegNext(fflagsEn))
118  val fflagsAll = Wire(Vec(8, UInt(5.W)))
119  fflagsAll := vfcvtFflags.asTypeOf(fflagsAll)
120  val fflags = fflagsEnCycle2.zip(fflagsAll).map{case(en, fflag) => Mux(en, fflag, 0.U(5.W))}.reduce(_ | _)
121  io.out.bits.res.fflags.get := fflags
122
123
124  /**
125   * [[mgu]]'s in connection
126   */
127  val resultDataUInt = Wire(UInt(dataWidth.W))
128  resultDataUInt := vfcvtResult
129
130  mgu.io.in.vd := resultDataUInt
131  mgu.io.in.oldVd := outOldVd
132  mgu.io.in.mask := maskToMgu
133  mgu.io.in.info.ta := outVecCtrl.vta
134  mgu.io.in.info.ma := outVecCtrl.vma
135  mgu.io.in.info.vl := Mux(outVecCtrl.fpu.isFpToVecInst, 1.U, outVl)
136  mgu.io.in.info.vlmul := outVecCtrl.vlmul
137  mgu.io.in.info.valid := io.out.valid
138  mgu.io.in.info.vstart := Mux(outVecCtrl.fpu.isFpToVecInst, 0.U, outVecCtrl.vstart)
139  mgu.io.in.info.eew := outEew
140  mgu.io.in.info.vsew := outVecCtrl.vsew
141  mgu.io.in.info.vdIdx := outVecCtrl.vuopIdx
142  mgu.io.in.info.narrow := RegNext(RegNext(isNarrowCvt))
143  mgu.io.in.info.dstMask := outVecCtrl.isDstMask
144
145  io.out.bits.res.data := mgu.io.out.vd
146}
147
148class VectorCvtTopIO(vlen: Int, xlen: Int) extends Bundle{
149  val uopIdx = Input(Bool())
150  val src = Input(Vec(vlen / xlen, UInt(xlen.W)))
151  val opType = Input(UInt(8.W))
152  val sew = Input(UInt(2.W))
153  val rm = Input(UInt(3.W))
154  val outputWidth1H = Input(UInt(4.W))
155  val isWiden = Input(Bool())
156  val isNarrow = Input(Bool())
157
158  val result = Output(UInt(vlen.W))
159  val fflags = Output(UInt((vlen/16*5).W))
160}
161
162
163
164//according to uopindex, 1: high64 0:low64
165class VectorCvtTop(vlen: Int, xlen: Int) extends Module{
166  val io = IO(new VectorCvtTopIO(vlen, xlen))
167
168  val (uopIdx, src, opType, sew, rm, outputWidth1H, isWiden, isNarrow) = (
169    io.uopIdx, io.src, io.opType, io.sew, io.rm, io.outputWidth1H, io.isWiden, io.isNarrow
170  )
171
172  val in0 = Mux(isWiden,
173    Mux(uopIdx, src(1).tail(32), src(0).tail(32)),
174    src(0)
175  )
176
177  val in1 = Mux(isWiden,
178    Mux(uopIdx, src(1).head(32), src(0).head(32)),
179    src(1)
180  )
181
182  val vectorCvt0 = Module(new VectorCvt(xlen))
183  vectorCvt0.src := in0
184  vectorCvt0.opType := opType
185  vectorCvt0.sew := sew
186  vectorCvt0.rm := rm
187
188  val vectorCvt1 = Module(new VectorCvt(xlen))
189  vectorCvt1.src := in1
190  vectorCvt1.opType := opType
191  vectorCvt1.sew := sew
192  vectorCvt1.rm := rm
193
194  val isNarrowCycle2 = RegNext(RegNext(isNarrow))
195  val outputWidth1HCycle2 = RegNext(RegNext(outputWidth1H))
196
197  //cycle2
198  io.result := Mux(isNarrowCycle2,
199    vectorCvt1.io.result.tail(32) ## vectorCvt0.io.result.tail(32),
200    vectorCvt1.io.result ## vectorCvt0.io.result)
201
202  io.fflags := Mux1H(outputWidth1HCycle2, Seq(
203    vectorCvt1.io.fflags ## vectorCvt0.io.fflags,
204    Mux(isNarrowCycle2, vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10), vectorCvt1.io.fflags ## vectorCvt0.io.fflags),
205    Mux(isNarrowCycle2, vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0), vectorCvt1.io.fflags.tail(10) ## vectorCvt0.io.fflags.tail(10)),
206    vectorCvt1.io.fflags(4,0) ## vectorCvt0.io.fflags(4,0)
207  ))
208}
209
210
211